IS62WV6416DBLL-45TLI

IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 35ns, 45ns, 55ns • CMOS low power operation: 15 mW (typical) operating 1.5 µW (typical) CMOS standby • TTL compatible interface levels DESCRIPTION The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL are high-speed, 1M bit static RAMs organized as 64K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • Single power supply 1.65V--2.2V Vdd (62WV6416DALL) DECEMBER 2012 2.3V--3.6V Vdd (65WV6416DBLL) Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and automotive temperature support • 2CS Option Available The IS62/65WV6416DALL and IS62/65WV6416DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB LB COLUMN I/O CONTROL CIRCUIT Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) 48-Pin mini BGA (6mm x 8mm) (Package Code B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 NC A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CSI I/O0 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A15 I/O0-I/O15 CS1, CS2 OE WE LB UB NC Vdd GND 2 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 44-Pin mini TSOP (Type II) (Package Code T) A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Vdd Current Not Selected X H X X X X High-Z High-Z Isb1, Isb2 X X L X X X High-Z High-Z Isb1, Isb2 X X X X H H High-Z High-Z Isb1, Isb2 Output Disabled H L H H L X High-Z High-Z Icc H L H H X L High-Z High-Z Icc Read H L H L L H Dout High-Z Icc H L H L H L High-Z Dout H L H L L L Dout Dout Write L L H X L H Din High-Z Icc L L H X H L High-Z Din L L H X L L Din Din ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 3 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL AC TEST CONDITIONS Parameter Unit Unit (2.3V-3.6V) (3.3V + 5%) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 317 317 R2 ( Ω ) 351 351 Vtm (V) 3.3V 3.3V Unit (1.65V-2.2V) 0.4V to Vdd - 0.3V 1V/ ns 0.9V See Figures 1 and 2 13500 10800 1.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 4 R2 5 pF Including jig and scope R2 Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1 mA Vdd = Min., Iol = 2.1 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.3V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 2.1 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.8 — 2.0 –0.3 –1 –1 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Vdd Ioh = -0.1 mA 1.65-2.2V Iol = 0.1 mA 1.65-2.2V 1.65-2.2V 1.65-2.2V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.4 — V — 0.2 V 1.4 Vdd + 0.2 V –0.2 0.4 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 5 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL OPERATING RANGE (Vdd) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 55ns 55ns Vdd (45 ns) 2.3V-3.6V 2.3V-3.6V Vdd (35 ns) 3.3V+5% 3.3V+5% OPERATING RANGE (Vdd) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERATING RANGE (Vdd) Range Ambient Temperature Automotive –40°C to +125°C Vdd (45 ns) 2.3V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -35 -45 -55 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. — 8 — 6 — 5 mA Supply Current Iout = 0 mA, f = fmax Ind. — 12 — 8 — 7 CE = Vil Auto. — 15 — 12 — 12 Vin ≥ Vdd – 0.3V, or typ.(2) 5 Vin ≤ 0.4V Icc1 Operating Vdd = Max., Com. — 2.5 — 2.5 — 2.5 mA Supply Current Iout = 0 mA, f = 0 Ind. — 2.5 — 2.5 — 2.5 CE = Vil Auto. — 5 — 5 — 5 Vin ≥ Vdd – 0.3V, or Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. — 2 — 2 — 2 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V, Ind. — 4 — 4 — 4 CS2 ≤ 0.2V, Auto — 18 — 18 — 18 Vin ≥ Vdd – 0.2V, or typ.(2) 0.6 Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tacs1/tacs2 tdoe thzoe(2) tlzoe(2) thzcs1/thzcs2(2) tlzcs1/tlzcs2(2) Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output 35 ns Min. Max. 35 — — 35 10 — — 35 — 10 0 10 3 — 0 10 5 — 45 ns Min. Max. 45 — — 45 10 — — 45 — 20 0 15 5 — 0 15 5 — 55 ns Min. Max. 55 — — 55 10 — — 55 — 25 0 20 5 — 0 20 10 — tba LB, UB Access Time — 35 — 45 — 55 ns thzb LB, UB to High-Z Output 0 15 0 15 0 20 ns tlzb LB, UB to Low-Z Output 0 — 0 — 0 — ns Unit ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 7 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE CS1 tLZOE tACE1/tACE2 CS2 tLZCE1/ tLZCE2 tHZCS1/ tHZCS2 LB, UB tLZB DOUT tBA tHZB HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc tscs1/tscs2 taw tha tsa tpwb tpwe tsd thd thzwe(3) tlzwe(3) 35 ns Min. Max. 45 — 35 — 35 — 0 — 0 — 35 — 35 — 20 — 0 — — 20 5 — Parameter Write Cycle Time CS1/CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output 45 ns Min. Max. 45 — 35 — 35 — 0 — 0 — 35 — 35 — 20 — 0 — — 20 5 — 55 ns Min. Max. 55 — 45 — 45 — 0 — 0 — 45 — 40 — 25 — 0 — — 20 5 — Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 9 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 10 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. Ind. Auto. tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform o Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Min. typ.(1) Max. Unit 1.2 3.6 V — 0.4 2 µA 4 18 0 — ns trc — ns DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CS2 tSDR tRDR VDR CS2 ≤ 0.2V GND 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL ORDERING INFORMATION IS62WV6416DALL (1.65V - 2.2V) Industrial Range: -40°C to +85°C Speed (ns) 55 Order Part No. IS62WV6416DALL-55BLI IS62WV6416DALL-55TLI Package mini BGA (6mm x 8mm), Lead-free TSOP TYPE II, Lead-free IS62WV6416DBLL (2.3V-3.6V) Industrial Range: -40°C to +85°C Speed (ns) 45 (35)1 Order Part No. IS62WV6416DBLL-45TI IS62WV6416DBLL-45TLI IS62WV6416DBLL-45BI IS62WV6416DBLL-45BLI IS62WV6416DBLL-45B2LI Package TSOP TYPE II TSOP TYPE II, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2CS, Lead-free Note: 1. Speed = 35ns for Vdd = 3.3V±5%. Speed = 45ns for Vdd = 2.3V-3.6V IS65WV6416DBLL (2.3V-3.6V) Automotive Range: -40°C to +125°C Speed (ns) 45 Order Part No. IS65WV6416DBLL-45CTLA3 IS65WV6416DBLL-45BLA3 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 Package TSOP TYPE II, Lead-free, Copper Lead-frame mini BGA (6mm x 8mm), Lead-free 13 14 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/18/12 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 15