IS62WVS5128FALL-16NLI-TR

IS62/65WVS5128FALL IS62/65WVS5128FBLL JULY 2021 512Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES • SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode • Low-Power CMOS Technology: - Read Current: 16 mA(max) at 3.6V, 20 MHz, 85°C - CMOS Standby Current: 8 A(typ) • 512K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential mode for Reads and Writes • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Automotive (A3): -40C to +125C • RoHS Compliant - 8-pin SOIC package DESCRIPTION The ISSI IS62/65WVS5128FALL/FBLL are 4M bit Serial static RAMs organized as 512K bytes by 8 bits. It is a dual die stack of two 2Mb Serial SRAMs. The device is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access the device is controlled through a Chip Select (CS#) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The IS62/65WVS5128FALL/FBLL are available in the standard 8-pin SOIC package. Copyright © 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 1 IS62/65WVS5128FALL IS62/65WVS5128FBLL BLOCK DIAGRAM SI (SIO0) SI (SIO0) SO (SIO1) SO (SIO1) DNU (SIO2) HOLD# (SIO3) Die 0 DNU (SIO2) HOLD# (SIO3) CS# CS# SCK SCK VSS VSS VDD VDD SI (SIO0) SO (SIO1) Die 1 DNU (SIO2) HOLD# (SIO3) CS# VSS VDD SCK Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 2 IS62/65WVS5128FALL IS62/65WVS5128FBLL PIN CONFIGURATIONS 8-pin SOIC PIN DESCRIPTIONS CS# 1 8 SO(SIO1) 2 7 DNU(SIO2) 3 6 4 5 VSS VDD HOLD# (SIO3) SCK CS# SO/SIO1 DNU/SIO2 VSS SI/SIO0 SCK HOLD#/SIO3 VDD Chip Enable Input Serial Output/SIO1 Do Not Use/SIO2 Ground Serial Input/SIO0 Serial Clock HOLD#/SIO3 Power SI (SIO0) Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 3 IS62/65WVS5128FALL IS62/65WVS5128FBLL Chip Select (CS#) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high- impedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS# is required, prior to any sequence being initiated. Serial Clock (SCK) The SCK is used to synchronize the communication between a master and Serial SRAM. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. Serial Output (SO: SPI mode) The SO pin is used to transfer data out of the device. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. Serial Input (SI: SPI mode) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. HOLD Function (HOLD#: SPI Mode, and SDI Mode) The HOLD# pin is used to suspend transmission to Serial SRAM while in the middle of a serial sequence without having to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD# pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD# pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The device must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD# should be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to low transition of the HOLD# pin, and will begin outputting again Immediately upon a subsequent low- to-high transition of the HOLD pin, independent of the state of SCK. Hold functionality is not available when operating in Quad SPI mode Serial Input / Output Pins (SIO0, SIO1: SDI Mode) The SIO0 and SIO1 pins are used for Dual SPI mode of operation (SI→SIO0, SO-->SIO1). Functionality of these I/O pins is shared with SO and SI. Serial Input / Output Pins (SIO0, SIO1, SIO2, SIO3: SQI Mode) The SIO0 through SIO3 pins are used for Quad SPI mode of operation. Because of the shared functionality of these pins the HOLD# feature is not available when using Quad SPI mode (Hold# →SIO3 in Quad SPI mode) DNU/SIO2 (Do Not Use or SIO2) Pin 3 is DNU (Do No Use) in SPI mode and SDI mode. SIO2 in SQI mode. Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 4 IS62/65WVS5128FALL IS62/65WVS5128FBLL FUNCTION DESCRIPTION Serial SRAM is designed to interface directly with the Serial Peripheral Interface (SPI). It can also interface with MultiIO SPI interface (Dual SPI and Quad SPI). The device contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS# pin must be low for the entire operation. All instructions, addresses and data are transferred MSB first, LSB last. OPERATION MODE The device has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Sequential. Byte Operation Byte Operation is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks. Page Operation Page Operation is selected when bits 7 and 6 in the MODE register are set to 10. The device has 16,384 pages of 32 bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page. Sequential Operation Sequential Operation is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented until reaches the end of die boundary. The device is stacked with 2-die, so it has a restriction in sequential operation: The address counter cannot cross the die boundary. When the Address Pointer reaches the highest address of first die (3FFFFh), the address counter cannot cross to first address of 2nd die (40000h). Instead, it rolls over to (00000h). So the sequential operation must be terminated at the last address of first die (Die 0) by CS# HIGH, and begin new sequential operation from first address (40000h) of second die (Die 1) by CS# LOW. MEMORY ARRAY SEGMENTS 00000h Die 0 3FFFFh X Sequential operation is not allowed to cross die boundary 40000h Die 1 7FFFFh Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 5 IS62/65WVS5128FALL IS62/65WVS5128FBLL WRITE MODE Prior to any attempt to write data to the device, the device must be selected by bringing CS# low. Once the device is selected, the Write command can be started by issuing a WRITE instruction, followed by the 24-bit address, with the first five MSB’s of the address being a “don’t care” bit, and then the data to be written. A write is terminated by the CS# being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the Device. The internal Address Pointer is automatically incremented until reaches to die boundary address. READ MODE The device is selected by pulling CS# Low. Then 8 bit instruction is transmitted to the device followed by the 24 bit address, with the first five MSB’s of the address being a “don’t care” bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses until reaches to die boundary address. Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 6 IS62/65WVS5128FALL IS62/65WVS5128FBLL INSTRUCTION SET Instruction Format Hex Code READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address ESDI 0011 1011 0x3B Enter SDI mode ESQI 0011 1000 0x38 Enter SQI mode RSTDQI 1111 1111 0xFF Reset SDI/SQI mode RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register Instruction Name Description BYTE READ OPERATION (SPI MODE) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 1 0 32 33 35 34 36 37 38 39 SCK ... 24-bit Address Instruction = 03h SI 0 0 0 0 0 0 1 1 23 22 ..... 2 Data Out SO High Impedance ..... tV 7 6 5 3 4 0 1 2 BYTE WRITE OPERATION (SPI MODE) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 2 1 0 SCK ... 24-bit Address Instruction = 02h SI 0 SO 0 0 0 0 0 1 0 23 22 ..... 2 Data Byte 1 0 7 6 5 4 3 High Impedance Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 7 IS62/65WVS5128FALL IS62/65WVS5128FBLL PAGE READ OPERATION (SPI MODE) CS# 0 1 2 3 4 5 7 6 8 9 29 30 31 32 33 35 34 36 37 38 39 SCK ... SI 0 0 0 0 0 ... 24-bit Address Instruction = 03h 1 0 23 1 ..... 22 2 ... 1 0 ... Page X, Word Y SO High Impedance Data Out ..... 7 tV 6 5 3 4 0 1 2 ... CS# ..... 40 41 42 43 44 45 47 46 SCK ... SI Page X, Word Y+1 Page X, Word 31 SO 7 6 5 3 4 ... 0 1 2 7 6 5 3 4 Page X, Word 0 0 1 2 7 6 5 3 4 2 1 0 1 0 PAGE WRITE OPERATION (SPI MODE) CS# 0 1 2 3 4 5 7 6 8 9 29 30 31 32 33 35 34 36 37 38 39 2 1 0 SCK ... 24-bit Address Instruction = 02h SI 0 0 SO 0 0 0 0 46 47 23 0 1 ..... 22 2 Data Byte 1 0 7 6 5 3 4 High Impedance CS# ..... 40 41 42 43 44 45 SCK ... Page X, Word 31 Page X, Word Y+1 SI 7 SO 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 Page X, Word 0 1 0 7 6 5 4 3 2 High Impedance Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 8 IS62/65WVS5128FALL IS62/65WVS5128FBLL SEQUENTIAL READ OPERATION (SPI MODE) CS# 0 1 2 3 4 5 7 6 8 9 29 30 31 32 33 35 34 36 37 38 39 SCK ... SI 0 0 0 0 0 ... 24-bit Address Instruction = 03h 1 0 23 1 ..... 22 2 ... 1 0 ... Page X, Word Y SO CS# High Impedance Page X, Word Y ..... tV 7 6 5 4 3 2 1 0 ... ... ..... SCK ... ... ... ... SI ... ... ... Page X, Word 31 ... SO 0 CS# 7 6 5 4 3 Page X+1, Word 0 2 1 0 7 6 5 4 3 2 Page X+1, Word 1 1 0 7 6 5 4 3 ... 2 1 0 ... ... ... ... SCK ... ... SI SO ... Page X+n, Word 29 ... 0 7 6 5 4 3 2 Page X+n, Word 30 1 0 7 6 5 4 3 2 Page X+n, Word 31 1 0 7 6 5 4 3 2 1 0 ... Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 9 IS62/65WVS5128FALL IS62/65WVS5128FBLL SEQUENTIAL WRITE OPERATION (SPI MODE) CS# 0 1 2 3 4 5 7 6 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK ... SI 0 0 0 0 0 ... 24-bit Address Instruction = 02h 1 0 23 1 ..... 22 2 Data Byte 1 1 0 7 6 5 3 4 ... 0 1 2 ... Page X, Word Y SO High Impedance CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK ... Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 7 6 5 4 3 Data Byte n 2 1 0 ... 7 6 5 4 3 2 1 0 10 IS62/65WVS5128FALL IS62/65WVS5128FBLL READ MODE REGISTER INSTRUCTION (RDMR) The Read Mode Register instruction (RDMR: 05h) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: . 7 6 W/R 5 4 3 2 1 0 – – – – – – MODE Reserved W/R = writable/readable The mode bits (7:6) indicate the operating mode of the SRAM. The possible modes of operation are: 0 0= Byte mode 1 0= Page mode 0 1= Sequential mode (default operation) 1 1= Reserved Bits 0 through 5 are reserved and should always be set to ‘0’. READ MODE REGISTER OPERATION TIMING (RDMR) CS# 0 1 2 3 4 5 6 7 0 1 8 9 10 11 12 13 14 15 1 0 SCK Instruction = 05h SI 0 0 0 0 0 1 Data from Mode register SO High Impedance Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 7 6 5 4 3 2 11 IS62/65WVS5128FALL IS62/65WVS5128FBLL WRITE MODE REGISTER INSTRUCTION (WRMR) The Write Mode Register instruction (WRMR: 01h) allows the user to write to the bits in the MODE register. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. WRITE MODE REGISTER OPERATION TIMING (WRMR) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction = 01h Data to Mode register SI 0 0 0 SO 0 0 0 0 1 7 6 5 4 3 2 High Impedance SDI MODE AND SQI MODE OPERATION The device also supports SDI (Serial Dual Interface) and SQI (Serial Quad Interface) mode of operation when used with compatible master devices. To enter SDI mode, the ESDI command (3Bh) must be clocked in. As a convention for SDI mode of operation, two bits are entered per clock using the SIO0 and SIO1 pins. Bits are clocked MSB first. To enter SQI mode, the ESQI command (38h) must be clocked in. For SQI mode of operation, four bits of data are entered per clock, or one nibble per clock. The nibbles are clocked MSB first. SPI Mode CS# SQI Mode SDI Mode VCC CS# VCC CS# VCC HOLD# SIO1 HOLD# SIO1 SIO3 DNU SCK DNU SCK SIO2 SCK VSS SI VSS SIO0 VSS SIO0 SO Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 12 IS62/65WVS5128FALL IS62/65WVS5128FBLL Enter SDI Mode Enter SQI Mode CS# CS# 0 1 2 3 4 5 6 7 0 SCK 1 2 3 4 5 6 7 0 0 SCK Instruction = 3Bh Instruction = 38h SI 0 0 1 SO 1 1 0 1 High Impedance 1 7 SI 0 SO 0 1 1 1 0 7 High Impedance To exit from SDI mode, the RSTDQI command (FFh) must be issued. The command must be entered in the current device configuration, either SDI mode or SQI mode. Reset SDI Mode Reset SQI Mode CS# CS# 0 0 1 2 1 3 SCK SCK FFh Instruction = FFh SIO0 1 SIO1 1 1 SIO0 SIO1 1 1 1 1 1 1 1 1 1 1 1 1 1 SIO2 SIO3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 13 IS62/65WVS5128FALL IS62/65WVS5128FBLL SDI (SERIAL DUAL INTERFACE) MODE OPERATION The device supports Serial Dual Interface (SDI) mode of operation. There are 4.0 clock cycles (Dummy Byte) of Read Latency in SDI mode Byte Read Operation. No Write Latency in SDI Write Operation. It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte Read Operation in SDI Mode CS# 0 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 SCK SIO0 SIO1 0 0 0 1 0 0 0 1 Read Latency = 4.0 clocks 24-bit Address Instruction = 03h 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Byte Write Operation in SDI Mode CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCK SIO0 SIO1 0 0 0 0 0 0 0 1 Data Byte 24-bit Address Instruction = 02h 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 14 IS62/65WVS5128FALL IS62/65WVS5128FBLL Byte Read Operation in SQI Mode CS# 0 1 2 3 4 5 6 8 7 9 10 11 SCK SIO0 SIO1 SIO2 SIO3 2.0 clocks 24-bit Address 03h 0 1 0 1 0 0 0 0 20 16 12 8 4 0 4 0 21 17 13 9 5 1 5 1 22 18 14 10 6 2 6 2 23 19 15 11 7 3 7 3 Byte Write Operation in SQI Mode CS# 0 1 2 3 4 5 6 7 8 9 SCK 24-bit Address 02h SIO0 SIO1 SIO2 SIO3 0 0 0 1 0 0 0 0 20 16 12 8 4 0 4 0 21 17 13 9 5 1 5 1 22 18 14 10 6 2 6 2 23 19 15 11 7 3 7 3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 15 IS62/65WVS5128FALL IS62/65WVS5128FBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Vter m tBIAS VDD Parameter Terminal Voltage with Respect to GND Temperature Under Bias V DD Related to GND Value –0.2 to +3.9(VDD+0.3V) –55 to +125 –0.2 to +3.9(VDD+0.3V) Unit V tStg Storage Temperature –65 to +150 C C V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (1) Range Industrial Industrial Automotive Note: 1. Device Marking IS62WVS5128FALL IS62WVS5128FBLL IS65WVS5128FBLL Ambient Temperature -40C to +85C -40C to +85C -40C to +125C VDD 1.65V-2.2V 2.2V-3.6V 2.2V-3.6V Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE (1) Parameter Input capacitance ( CS#, SCK) Input/Output capacitance (other pins) Symbol CIN CI/O Test Condition TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max 12 16 Units pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 16 IS62/65WVS5128FALL IS62/65WVS5128FBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Unit (1.65V~2.2V) 0V to VDD Unit (2.2V~2.7V) 0V to VDD Unit (2.7V~3.6V) 0V to VDD Input Rise and Fall Time 1V/ns 1V/ns 1V/ns Output Timing Reference Level 0.9V ½ VDD ½ VDD R1 13500 16667 1103 R2 10800 15385 1554 VTM 1.8V VDD VDD Parameter Input Pulse Level Output Load Conditions Refer to Figure 1 and 2 OUTPUT LOAD CONDITIONS FIGURES Figure1 Figure2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, includin g jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 R2 5pF, includin g jig and scope R2 17 IS62/65WVS5128FALL IS62/65WVS5128FBLL ELECTRICAL CHARACTERISTICS IS62WVS2568FALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD=1.65V~2.2V Symbol VOH VOL VIH(1) VIL(1) VDR(2) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Data Retention Voltage Input Leakage Output Leakage Test Conditions IOH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 1.4 –0.2 –1 –1 Typ. 1.0 - Max. 0.2 VDD + 0.2 0.4 1 1 Unit V V V V V µA µA Notes: 1. VILL (min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. 2. This is the limit to which VDD can be lowered without losing RAM data at TA = 25C. This parameter is periodically sampled and not 100% tested. IS62 (5) WVS2568FBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD=2.2V~3.6V Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VIH(1) Input HIGH Voltage VIL(1) Input LOW Voltage VDR(2) ILI ILO Data Retention Voltage Input Leakage Output Leakage Test Conditions 2.2 ≤ VDD < 2.7, IOH = -0.1 mA 2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA 2.2 ≤ VDD < 2.7, IOL = 0.1 mA 2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 2.2 ≤ VDD < 2.7 2.7 ≤ VDD ≤ 3.6 GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.0 2.4 1.8 2.2 –0.3 –0.3 –1 –1 Typ. 1.0 - Max. 0.4 0.4 VDD + 0.3 VDD + 0.3 0.6 0.8 1 1 Unit V V V V V V V V V µA µA Notes: 1. VILL (min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. 2. This is the limit to which VDD can be lowered without losing RAM data at TA = 25C. This parameter is periodically sampled and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 18 IS62/65WVS5128FALL IS62/65WVS5128FBLL IS62WVS5128FALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter Test Conditions Grade Typ. ICC VDD Dynamic Operating Supply Current CMOS Standby Current (CMOS Inputs) ISB2 Note: 1. VDD = Max , f = fMAX , CS# = VIL IOUT = 0 mA Com. VDD = Max, f = 0, CS# ≥ VDD 0.2V VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Com. Ind. Ind. - 8 -16 Max. 14 16 Unit mA 20 µA 40 µA Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at TA = 25C IS62(5)WVS5128FBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter Test Conditions Grade -20 Max. 14 16 26 20 Typ. ICC ISB2 Note: 1. VDD Dynamic Operating Supply Current CMOS Standby Current (CMOS Inputs) VDD = Max , f = fMAX , CS# = VIL IOUT = 0 mA VDD = Max, f = 0 CS# ≥ VDD - 0.2V VIN ≤ 0.2V or VIN ≥ VDD - 0.2V Com. Ind. Auto. Com. Ind. Auto. 8 40 72 Typ. - - -16 Max. 14 16 26 20 Unit mA µA 40 µA 72 µA Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at TA = 25℃ Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 19 IS62/65WVS5128FALL IS62/65WVS5128FBLL AC CHARACTERISTICS (1) (OVER OPERATING RANGE) READ/WRITE CYCLE AC CHARACTERISTICS Parameter Symbol Clock Frequency CS# Setup Time CS# Hold Time CS# Disable Time Data Setup Time Data Hold Time Clock High Time Clock Low Time Clock Delay Time Output Valid from Clock Low Output Hold Time CS# High to Output High-Z HOLD# Setup Time HOLD# Hold Time HOLD# Low to Output High-Z HOLD# High to Output Valid FCLK tCSS tCSH tCSD tDS tDH tCKH tCKL tCLD tV tOH tCHZ tHS tHH tHZ tHV -20 Min 25 50 25 10 10 23 23 25 0 10 10 - -16 Max 20 25 20 20 50 Min 32 50 32 10 10 32 32 32 0 10 10 - Max 16 36 20 20 50 unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns notes 1 1 1 Note: 1. Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 20 IS62/65WVS5128FALL IS62/65WVS5128FBLL TIMING DIAGRAM Serial Input/Output Timing (SPI Mode) tCSD CS# tCSS CSH tCKH SCK tDS tCKL tDH VALID INPUT SI VALID INPUT tV SO tCLD HI-Z Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 tCHZ tOH VALID OUTPUT HI-Z 21 IS62/65WVS5128FALL IS62/65WVS5128FBLL HOLD Timing (SPI Mode) CS# tHH tR tF tHS tHH tHS SCK tHZ tHV SO SI HOLD# Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 22 IS62/65WVS5128FALL IS62/65WVS5128FBLL ORDERING INFORMATION IS62WVS5128FALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (MHz) 16 Order Part No. Package IS62WVS5128FALL-16NLI 8-pin SOIC 150mil, Lead-free IS62WV5128FBLL (2.2V - 3.6V) Industrial Range: –40°C to +85°C Speed (MHz) Order Part No. Package 20 IS62WVS5128FBLL-20NLI 8-pin SOIC 150mil, Lead-free 16 IS62WVS5128FBLL-16NLI 8-pin SOIC 150mil, Lead-free Automotive Range (A3): –40°C to +125°C Speed (MHz) 16 Order Part No. Package IS65WVS5128FBLL-16NLA3 8-pin SOIC 150mil, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 23 IS62/65WVS5128FALL IS62/65WVS5128FBLL PACKAGE INFORMATION 8-Pin SOIC 150MIL Package (N) Integrated Silicon Solution, Inc.- www.issi.com Rev. A8 07/06/2021 24