IS63WV1288DBLL-10HLI

IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS63/64WV1288DALL/DBLL) • High-speed access time: 8, 10, 12, 20 ns • Low Active Power: 135 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby LOW POWER: (IS63/64WV1288DALS/DBLS) • High-speed access time: 25, 35 ns • Low Active Power: 55 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby • Single power supply — Vdd 1.65V to 2.2V (IS63WV1288DAxx) — Vdd 2.4V to 3.6V (IS63/64WV1288DBxx) • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Lead-free available JUNE 2021 DESCRIPTION The ISSI IS63/64WV1288Dxxx is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM. The IS63/64WV1288DBLL is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 25 µW (typical) with CMOS input levels. The IS63/64WV1288DBLL operates from a single Vdd power supply. The IS63/64WV1288Dxxx is available in 32-pin TSOP (Type II), 32-pin sTSOP (Type I), 48-Ball miniBGA (6mm x 8mm) and 32-pin SOJ (300-mil) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K X 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 CE OE COLUMN I/O CONTROL CIRCUIT WE Copyright © 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type II) (T) 32-Pin sTSOP (Type I) (H) A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 VDD 8 25 GND GND 9 24 VDD I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN DESCRIPTIONS A0-A16 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Vdd Power GND Ground 2 A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 PIN CONFIGURATION 48-mini BGA (B) (6 mm x 8 mm) 1 2 3 4 5 6 A NC OE A2 A6 A7 NC B I/O0 NC A1 A5 CE I/O7 C I/O1 NC A0 A4 NC I/O6 D GND NC NC A3 NC VDD E VDD NC NC NC NC GND F I/O2 NC A14 A11 I/O4 I/O5 G I/O3 NC A15 A12 WE A8 H NC A10 A16 A13 A9 NC Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z Vdd Current Isb1, Isb2 High-Z Dout Din Icc1, Icc2 Icc1, Icc2 Icc1, Icc2 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Tstg Storage Temperature Pt Power Dissipation Vdd Vdd Related to GND Value Unit –0.5 to Vdd+0.5 V –65 to +150 °C 1.5 W -0.2 to +3.9 V Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS AC TEST CONDITIONS Parameter Unit Unit Unit (2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 0.9V and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 1909 317 13500 R2 ( Ω ) 1105 351 10800 Vtm (V) 3.0V 3.3V 1.8V AC TEST LOADS R1 ZO = 50Ω 50Ω OUTPUT 30 pF Including jig and scope Figure 1. 4 VTM VDD/2 OUTPUT 5 pF Including jig and scope R2 Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA Output LOW Voltage Vdd = Min., Iol = 8.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 2.4 — V — 0.4 V 2 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Test Conditions Vdd Min. Max. Unit Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V 1.4 — V Output LOW Voltage Iol = 0.1 mA 1.65-2.2V — 0.2 V Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V Input LOW Voltage 1.65-2.2V –0.2 0.4 V Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS HIGH SPEED (IS63WV1288DALL/DBLL) OPERATING RANGE (Vdd) (IS63WV1288DALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 20ns 20ns 20ns OPERATING RANGE (Vdd) (IS63WV1288DBLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (8 ns)1 3.3V + 5% 3.3V + 5% Vdd (10 ns)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV1288DBLL)(2) Range Ambient Temperature Automotive –40°C to +125°C Vdd (8 ns)2 3.3V + 5% Vdd (10 ns)2 2.4V-3.6V Note: 2. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -12 -20 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. — 65 — 50 — 45 — 40 mA Supply Current Iout = 0 mA, f = fmax Ind. — 70 — 55 — 50 — 45 CE = Vil Auto.(3) — — — 65 — 55 — 50 Vin ≥ Vdd – 0.3V, or typ.(2) 45 45 Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. — 40 — 40 — 40 — 40 µA Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 55 — 55 — 55 — 55 Vin ≥ Vdd – 0.2V, or Auto. — — — 90 — 90 — 90 Vin ≤ 0.2V, f = 0 typ.(2) 4 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS LOW POWER (IS63WV1288DALS/DBLS) OPERATING RANGE (Vdd) (IS63WV1288DALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 55ns OPERATING RANGE (Vdd) (IS63WV1288DBLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (35 ns) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (Vdd) (IS64WV1288DBLS) Range Ambient Temperature Automotive –40°C to +125°C Vdd (35 ns) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -25 -35 -45 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. — 15 — 15 — 12 mA Supply Current Iout = 0 mA, f = fmax Ind. — 20 — 20 — 18 CE = Vil Auto. — 30 — 30 — 25 Vin ≥ Vdd – 0.3V, or typ.(2) 18 Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. — 40 — 40 — 40 µA Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 50 — 50 — 50 Vin ≥ Vdd – 0.2V, or Auto. — 75 — 75 — 75 Vin ≤ 0.2V, f = 0 typ.(2) 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit Cin Input Capacitance VIN = 0V 6 pF Ci/o Input/Output Capacitance VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 ns -10 ns -12 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 8 — 10 — 12 — ns taa Address Access Time — 8 — 10 — 12 ns toha Output Hold Time 2 — 2 — 2 — ns tace CE Access Time — 8 — 10 — 12 ns tdoe OE Access Time — 4 — 5 — 6 ns (2) tlzoe OE to Low-Z Output 0 — 0 — 0 — ns thzoe(2) OE to High-Z Output 0 4 0 5 0 6 ns (2) tlzce CE to Low-Z Output 3 — 3 — 3 — ns (2) thzce CE to High-Z Output 0 4 0 5 0 6 ns tpu CE to Power Up Time 0 — 0 — 0 — ns tpd CE to Power Down Time — 8 — 10 — 12 ns Notes: 1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V loading specified in Figure 1. 2.  Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tace tdoe thzoe(2) tlzoe(2) thzce tlzce(2) (2 Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output -20 ns -25 ns Min. Max. Min. Max. 20 — 25 — — 20 — 25 2.5 — 6 — — 20 — 25 — 8 — 12 0 8 0 8 0 — 0 8 3 — 0 — 0 8 10 — -35 ns -45 ns Min. Max. Min. Max. 35 — 45 — — 35 — 45 8 — 10 — — 35 — 45 — 15 — 20 0 10 0 15 0 — 0 10 10 — 0 — 0 15 10 — Unit ns ns ns ns ns ns ns ns ns Notes: 1.  Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2.  Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  Not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA DOUT t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 ns -10 ns -12 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time 8 — 10 — 12 — ns tsce CE to Write End 7 — 7 — 8 — ns taw Address Setup Time to 8 — 8 — 8 — ns Write End tha Address Hold from 0 — 0 — 0 — ns Write End tsa Address Setup Time 0 — 0 — 0 — ns (1) tpwe1 WE Pulse Width (OE High) 7 — 7 — 8 — ns (2) tpwe2 WE Pulse Width (OE Low) 8 — 10 — 12 — ns tsd Data Setup to Write End 5 — 5 — 6 — ns thd Data Hold from Write End 0 — 0 — 0 — ­ns thzwe(2) WE LOW to High-Z Output — 4 — 5 — 6 ns (2) tlzwe WE HIGH to Low-Z Output 3 — 3 — 3 — ns Notes: 1.  Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns -25 ns -35 ns Symbol Parameter Min. Max. Min. Max. Min. Max. twc Write Cycle Time 20 — 25 — 35 — tsce CE to Write End 12 — 18 — 25 — taw Address Setup Time 12 — 15 — 25 — to Write End tha Address Hold from Write End 0 — 0 — 0 — tsa Address Setup Time 0 — 0 — 0 — tpwe1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — tpwe2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — tsd Data Setup to Write End 9 — 12 — 15 — thd Data Hold from Write End 0 — 0 — ­ 0 — (3) thzwe WE LOW to High-Z Output — 9 — 12 — 20 (3) tlzwe WE HIGH to Low-Z Output 3 — 5 — 5 — -45ns Min. Max. 45 — 35 — 35 — Unit ns ns ns 0 — 0 — 35 — 35 — 20 — 0 — — 20 5 — ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2.  Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE tSA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS HIGH SPEED (IS63/4WV1288DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 4 40 µA Ind. — — 55 Auto. 90 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. o DATA RETENTION SWITCHING CHARACTERISTICS  (1.65V-2.2V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Com. — 4 40 µA Ind. — — 55 Auto. — — 90 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS LOW POWER (IS63/4WV1288DALS/DBLS) DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 4 40 µA Ind. — — 50 Auto. 75 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. o DATA RETENTION SWITCHING CHARACTERISTICS  (1.65V-2.2V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Com. — 4 40 µA Ind. — — 50 Auto. — — 75 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 14 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS ORDERING INFORMATION Industrial Range: –40°C to +85°C peed (ns) S 8 10 Order Part No. IS63WV1288DBLL-8TLI IS63WV1288DBLL-8HLI IS63WV1288DBLL-8JLI IS63WV1288DBLL-10TLI IS63WV1288DBLL-10HLI IS63WV1288DBLL-10JLI Package 32-pin TSOP (Type II), Lead-free sTSOP (Type I) (8mm x13.4mm), Lead-free 32-pin SOJ (300-mil), Lead-free 32-pin TSOP (Type II), Lead-free sTSOP (Type I) (8mm x13.4mm), Lead-free 32-pin SOJ (300-mil), Lead-free Automotive Range (A3): –40°C to +125°C peed (ns) S 10(8*) Order Part No. IS64WV1288DBLL-10CTLA3 IS64WV1288DBLL-10HLA3 Package 32-pin TSOP (Type II), Copper Lead frame, Lead-free sTSOP (Type I) (8mm x13.4mm), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V-3.6V. Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. B2 06/28/2021 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. B2 06/28/2021 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS Integrated Silicon Solution, Inc. — www.issi.com 19 Rev. B2 06/28/2021