IS64WV10248EDBLL-10BLA3

IS61WV10248EDBLL IS64WV10248EDBLL 1M x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Packages available: – 48-ball miniBGA (6mm x 8mm) – 44-pin TSOP (Type II) • Industrial and Automotive Temperature Support • Lead-free available APRIL 2020 DESCRIPTION The ISSI IS61/64WV10248EDBLL are very high-speed, low power, 1M-word by 8-bit CMOS static RAM. The IS61/64WV10248EDBLL are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. The IS61/64WV10248EDBLL operate from a single power supply and all inputs are TTL-compatible. The IS61/64WV10248EDBLL are available in 48 ball mini BGA (6mm x 8mm) and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A19 Memory Array (1024Kx8) Decoder 8 8 IO0-7 I/O Data Circuit /CE /OE /WE Control Circuit 8 ECC Array (1024Kx4) 4 12 ECC Column I/O Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL PIN CONFIGURATION 48-pin Mini BGA (B) (6mm x 8mm) 1 2 3 4 5 44-pin TSOP (Type II ) 6 A NC OE A0 A1 A2 NC B NC NC A3 A4 CE I/O0 C NC NC A5 A6 I/O1 I/O2 D GND NC A17 A7 I/O3 VDD E VDD NC NC A16 I/O4 GND F NC NC A14 A15 I/O5 I/O6 G NC NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 A19 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND VDD I/O5 I/O4 A14 A13 A12 A11 A10 A19 NC NC PIN DESCRIPTIONS A0-A19 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Data Input / Output Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL TRUTH TABLE Mode WE CE Not Selected X H (Power-down) Output Disabled H L Read H L Write L L OE I/O Operation Vdd Current X High-Z Isb1, Isb2 H L X High-Z Dout Din Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 6 pF 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL OPERATING RANGE (Vdd)1 Range Ambient Temperature Industrial –40°C to +85°C Automotive (A1) –40°C to +85°C Automotive (A3) –40°C to +125°C IS61WV10248EDBLL Vdd (8, 10ns) 2.4V-3.6V — — IS64WV10248EDBLL Vdd (10ns) — 2.4V-3.6V 2.4V-3.6V Note: 1. Contact SRAM@issi.com for 1.8V option ERROR DETECTION AND ERROR CORRECTION • • • • 4 Independent ECC with hamming code for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width ≤ 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width ≤ 2 ns). Not 100% tested. AC TEST CONDITIONS (HIGH SPEED) Parameter Unit (2.4V-3.6V) Input Pulse Level 0.4V to Vdd-0.3V Input Rise and Fall Times 1.5ns Input and Output Timing Vdd/2 and Reference Level (VRef) Output Load See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 5 pF Including jig and scope 353 Ω Figure 2. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 50 Supply Current Iout = 0 mA, f = fmax Ind. — 60 Auto. — — typ.(2) Icc1 Operating Vdd = Max., Com. — 20 Supply Current Iout = 0 mA, f = 0 Ind. — 25 Auto. — — Isb1 TTL Standby Current Vdd = Max., Com. — 20 (TTL Inputs) Vin = Vih or Vil Ind. — 25 CE ≥ Vih, f = 0 Auto. — — Isb2 CMOS Standby Vdd = Max., Com. — 10 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 15 Vin ≥ Vdd – 0.2V, or Auto. — — Vin ≤ 0.2V, f = 0 typ.(2) -10 Min. Max. — 45 — 55 — 65 15 — 20 — 25 — 50 — 20 — 25 — 45 — 10 — 15 — 35 2 -20 Min. Max. Unit — 35 mA — 45 — 60 — 20 mA — 25 — 50 — 20 mA — 25 — 45 — 10 mA — 15 — 35 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Min. Max. trc Read Cycle Time 8 — taa Address Access Time — 8 toha Output Hold Time 2.5 — tace CE Access Time — 8 tdoe OE Access Time — 5.5 thzoe(2) OE to High-Z Output — 3 tlzoe(2) OE to Low-Z Output 0 — thzce(2 CE to High-Z Output 0 3 (2) tlzce CE to Low-Z Output 3 — tpu Power Up Time 0 — tpd Power Down Time — 8 -10 Min. Max. Unit 10 — ns — 10 ns 2.5 — ns — 10 ns — 6.5 ns — 4 ns 0 — ns 0 4 ns 3 — ns 0 — ns — 10 ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Symbol Parameter Min. Max. Unit trc Read Cycle Time 20 — ns taa Address Access Time — 20 ns toha Output Hold Time 2.5 — ns tace CE Access Time — 20 ns tdoe OE Access Time — 8 ns (2) thzoe OE to High-Z Output 0 8 ns (2) tlzoe OE to Low-Z Output 0 — ns thzce(2 CE to High-Z Output 0 8 ns (2) tlzce CE to Low-Z Output 3 — ns tpu Power Up Time 0 — ns tpd Power Down Time — 20 ns Notes: 1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  Not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 -10 Symbol Parameter Min. Max. Min. Max. Unit twc Write Cycle Time 8 — 10 — ns tsce CE to Write End 6.5 — 8 — ns taw Address Setup Time 6.5 — 8 — ns to Write End tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwe1 WE Pulse Width (OE = HIGH) 6.5 — 8 — ns tpwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tsd Data Setup to Write End 5 — 6 — ns thd Data Hold from Write End 0 — 0 — ­ns (2) thzwe WE LOW to High-Z Output — 3.5 — 5 ns tlzwe(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter twc Write Cycle Time tsce CE to Write End taw Address Setup Time to Write End tha Address Hold from Write End tsa Address Setup Time tpwe1 WE Pulse Width (OE = HIGH) tpwe2 WE Pulse Width (OE = LOW) tsd Data Setup to Write End thd Data Hold from Write End (2) thzwe WE LOW to High-Z Output tlzwe(2) WE HIGH to Low-Z Output -20 ns Min. Max. Unit 20 — ns 12 — ns 12 — ns 0 0 12 17 9 0 — ns — ns — ns — ns — ns — ­ns — 3 9 ns — ns Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 12 t HD DATAIN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL AC WAVEFORMS WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN 14 t HD DATAIN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Vdr Typ.(1) Max. Unit Vdd for Data Retention See Data Retention Waveform 2.0 — Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 2 Ind. — — Auto. tsdr Data Retention Setup Time See Data Retention Waveform 0 — trdr Recovery Time See Data Retention Waveform trc — Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. 3.6 V 10 mA 15 35 — ns — ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. B 04/27/2020 IS61WV10248EDBLL IS64WV10248EDBLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 8 10 Order Part No. Package IS61WV10248EDBLL-8BLI 48 mini BGA (6mm x 8mm), Lead-free IS61WV10248EDBLL-8TLI TSOP (Type II), Lead-free IS61WV10248EDBLL-10BI 48 mini BGA (6mm x 8mm) IS61WV10248EDBLL-10BLI 48 mini BGA (6mm x 8mm), Lead-free IS61WV10248EDBLL-10TI TSOP (Type II) IS61WV10248EDBLL-10TLI TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 16 Order Part No. Package IS64WV10248EDBLL-10BA3 48 mini BGA (6mm x 8mm) IS64WV10248EDBLL-10BLA3 48 mini BGA (6mm x 8mm), Lead-free IS64WV10248EDBLL-10CTA3 TSOP (Type II), Copper Leadframe IS64WV10248EDBLL-10CTLA3 TSOP (Type II), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020 Rev. B 04/27/2020 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61WV10248EDBLL IS64WV10248EDBLL Integrated Silicon Solution, Inc. — www.issi.com 17 18 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV10248EDBLL IS64WV10248EDBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. B 04/27/2020