IS64WV12816DBLL-12CTA3

IS61WV12816DALL/DALS IS61WV12816DBLL/DBLS IS64WV12816DBLL/DBLS 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV12816DALL/DBLL) • High-speed access time: 8, 10, 12, 20 ns • Low Active Power: 135 mW (typical) • Low Standby Power: 12 μW (typical) CMOS standby LOW POWER: (IS61/64WV12816DALS/DBLS) • High-speed access time: 25, 35 ns • Low Active Power: 55 mW (typical) • Low Standby Power: 12 μW (typical) CMOS standby • Single power supply — VDD 1.65V to 2.2V (IS61WV12816DAxx) — VDD 2.4V to 3.6V (IS61/64WV12816DBxx) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available MAY 2008 DESCRIPTION The ISSI IS61WV12816DAxx/DBxx and IS64WV12816DBxx are high-speed, 2,097,152-bit static RAMs organized as 131,072 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 1 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS TRUTH TABLE I/O PIN Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O0-I/O7 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O8-I/O15 High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1, ISB2 ICC ICC Write ICC PIN CONFIGURATION 44-Pin TSOP (Type II) (T) PIN DESCRIPTIONS A0-A16 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground I/O0-I/O15 CE OE WE LB UB NC VDD GND A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS PIN CONFIGURATION 48-Pin mini BGA (B) 1 2 3 4 5 6 1 PIN DESCRIPTIONS A0-A16 I/O0-I/O15 CE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 NC OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 NC NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 NC I/O0 I/O2 VDD GND I/O6 I/O7 NC OE WE LB UB NC VDD GND Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 3 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions VDD = Min., IOH = –4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 1.0 mA Min. 1.8 — 2.0 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOL = 0.1 mA VDD 1.65-2.2V 1.65-2.2V 1.65-2.2V 1.65-2.2V Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load R1 ( Ω ) R2 ( Ω ) VTM (V) Unit (2.4V-3.6V) 0.4V to VDD - 0.3V 1V/ ns VDD /2 See Figures 1 and 2 1909 1105 3.0V Unit (3.3V + 5%) 0.4V to VDD - 0.3V 1V/ ns VDD + 0.05 2 See Figures 1 and 2 317 351 3.3V Unit (1.65V-2.2V) 0.4V to VDD - 0.3V 1V/ ns 0.9V See Figures 1 and 2 13500 10800 1.8V 1 2 3 4 AC TEST LOADS R1 5 6 R2 ZO = 50Ω OUTPUT 50Ω VDD/2 30 pF Including jig and scope VTM OUTPUT 5 pF Including jig and scope 7 8 9 10 11 12 Figure 1. Figure 2. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 5 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) OPERATING RANGE (VDD) (IS61WV12816DALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 20ns 20ns 20ns 1 2 3 4 5 2 OPERATING RANGE (VDD) (IS61WV12816DBLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS)1 3.3V + 5% 3.3V + 5% VDD (10 nS)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (VDD) (IS64WV12816DBLL)(2,3) Range Automotive Ambient Temperature –40°C to +125°C VDD (10 nS) 3.3V + 5% 2 VDD (12 nS) 2.4V-3.6V Note: 2. When operated in the range of 2.4V-3.6V, the device meets 12ns. When operated in the range of 3.3V + 5%, the device meets 10ns. 3. If the device is operated in the temperature range of -40oC to +85oC, the device meets 10ns. 6 7 POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. CE = VIL Auto.(3) VIN ≥ VDD – 0.3V, or typ.(2) VIN ≤ 0.4V VDD = Max., IOUT = 0 mA, f = 0 CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. -8 Min. Max. — — — 65 70 — -10 Min. Max. — — — 45 — — — 2 2 — — — — 2 2 2 — — — 60 65 75 -12 Min. Max. — — — 45 2 2 2 — — — 2 2 2 mA 55 55 60 -20 Min. Max. — — — 40 45 50 Unit mA (1) 8 9 10 11 12 ICC1 Operating Supply Current ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. Auto. typ.(2) — — — 50 70 — — — — 4 50 70 100 — — — 4 50 70 100 — — — 50 70 100 μA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 7 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) OPERATING RANGE (VDD) (IS61WV12816DALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 55ns OPERATING RANGE (VDD) (IS61WV12816DBLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (35 nS) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (VDD) (IS64WV12816DBLS) Range Automotive Ambient Temperature –40°C to +125°C VDD (35 nS) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V VDD = Max., IOUT = 0 mA, f = 0 CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) Com. Ind. Auto. -25 Min. Max. — — — 18 — — — 2 2 2 — — — 2 2 2 — — — 2 2 2 mA 20 25 40 -35 Min. Max. — — — 20 25 35 -45 Min. Max. — — — 18 20 30 Unit mA ICC1 Operating Supply Current ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. Auto. typ.(2) — — — 4 40 50 75 — — — 40 50 75 — — — 40 50 75 μA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time -8 Min. Max. 8 — 2.0 — — — 0 0 3 — 0 0 0 — — 8 — 8 5.5 3 — 3 — 5.5 5.5 — — 8 -10 Min. Max. 10 — 2.0 — — — 0 0 3 — 0 0 0 — — 10 — 10 6.5 4 — 4 — 6.5 6.5 — — 10 Min. 12 — 3 — — — 0 0 3 — 0 0 0 — -12 Max. — 12 — 12 6.5 6 — 6 — 6.5 6.5 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 4 5 6 7 8 9 10 11 12 tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 9 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -20 ns Min. Max. 20 — 2.5 — — 0 0 0 3 — 0 0 — 20 — 20 8 8 — 8 — 8 8 — -25 ns Min. Max. 25 — 6 — — 0 0 0 10 — 0 0 — 25 — 25 12 8 — 8 — 25 8 — -35 ns Min. Max. 35 — 8 — — 0 0 0 10 — 0 0 — 35 — 35 15 10 — 10 — 35 10 — -45 ns Min. Max. 45 — 10 — — 0 0 0 10 — 0 0 — 45 — 45 20 15 — 15 — 45 15 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE tLZCE tBA tHZB tLZB (2 (2) Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) 1 2 t OHA DATA VALID READ1.eps t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID 3 4 READ CYCLE NO. 2(1,3) tRC ADDRESS 5 6 tAA tOHA tDOE tHZOE OE 7 8 CE tLZOE tACE tLZCE tHZCE LB, UB DOUT HIGH-Z tLZB tBA tRC DATA VALID tHZB VDD Supply Current tPU 50% tPD ICC 50% 9 10 11 12 ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 11 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output (2) Min. 8 6.5 6.5 0 0 6.5 6.5 8.0 5 0 — 2 Max. — — — — — — — — — — 3.5 — -10 Min. Max. 10 8 8 0 0 8 8 10 6 0 — 2 — — — — — — — — — — 5 — Min. 12 9 9 0 0 9 9 11 9 0 — 3 -12 Max. — — — — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(2) tLZWE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output (3) -20 ns Min. Max. 20 12 12 0 0 12 12 17 9 0 — 3 — — — — — — — — — — 9 — -25 ns Min. Max. 25 18 15 0 0 18 18 20 12 0 — 5 — — — — — — — — — — 12 — -35 ns Min. Max. 35 25 25 0 0 30 30 30 15 0 — 5 — — — — — — — — — — 20 — -45ns Min. Max. 45 35 35 0 0 35 35 35 20 0 — 5 — — — — — — — — — — 20 — Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 4 5 6 7 8 9 10 11 12 tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE(3) tLZWE Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 13 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t PBW UB, LB t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS 1 2 t HA OE CE LOW LOW t AW t PWE2 WE 3 t LZWE t SA UB, LB t PBW t HZWE DOUT DATA UNDEFINED HIGH-Z 4 5 UB_CEWR3.eps t SD DIN t HD DATAIN VALID 6 WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS ADDRESS 1 7 8 t HA t WC ADDRESS 2 OE t SA CE LOW WE t HA t SA t PBW t PBW WORD 2 9 10 UB_CEWR4.eps UB, LB WORD 1 t HZWE DOUT HIGH-Z t LZWE t HD DATAIN VALID DATA UNDEFINED t SD DIN t SD DATAIN VALID t HD 11 12 Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 15 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V Com. Ind. Auto. Options Min. 2.0 — — 0 Typ.(1) — 10 — — — Max. 3.6 50 70 100 — — Unit V μ A VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform O ns ns tRC Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 1.2V, CE ≥ VDD – 0.2V Com. Ind. Auto. Options Min. 1.2 — — — 0 Typ.(1) — 10 — — — — Max. 3.6 50 70 100 — — Unit V μ A VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform O ns ns tRC Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD Data Retention Mode tRDR VDR CE ≥ VDD - 0.2V CE GND 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 2.0V, CE ≥ VDD – 0.2V Com. Ind. Auto. Options Min. 2.0 — — 0 Typ.(1) — 20 — — — Max. 3.6 40 50 75 — — Unit V μ A 1 2 3 4 Min. 1.2 — — — 0 Typ.(1) — 20 — — — — Max. 3.6 40 50 75 — — Unit V μ A VDR IDR tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform O ns ns tRC Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter VDD for Data Retention Data Retention Current Test Condition See Data Retention Waveform VDD = 1.2V, CE ≥ VDD – 0.2V Com. Ind. Auto. Options VDR IDR 5 6 7 8 tSDR tRDR Data Retention Setup Time Recovery Time See Data Retention Waveform See Data Retention Waveform O ns ns tRC Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR VDD Data Retention Mode tRDR 9 10 VDR CE ≥ VDD - 0.2V CE GND 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 17 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (HIGH SPEED) Commercial Range: 0°C to +70°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (8 ) 1 Order Part No. IS61WV12816DBLL-10TL Package TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (8 ) 1 Order Part No. IS61WV12816DBLL-10BI IS61WV12816DBLL-10BLI IS61WV12816DBLL-10TI IS61WV12816DBLL-10TLI Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. IS61WV12816DALL-20BI IS61WV12816DALL-20TI Package 48 mini BGA (6mm x 8mm) TSOP (Type II) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 12 (10 ) 2,3 Order Part No. IS64WV12816DBLL-12BA3 IS64WV12816DBLL-12BLA3 IS64WV12816DBLL-12CTA3 IS64WV12816DBLL-12CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Note: 2. Speed = 10ns for VDD = 3.3V + 5%. Speed = 12ns for VDD = 2.4V to 3.6V. 3. Speed = 10ns for VDD = 2.4V to 3.6V and temperature = -40oC to +85oC. 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (LOW POWER - IN EVALUATION) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 35 Order Part No. Package 1 2 3 4 5 6 7 8 9 10 11 12 IS61WV12816DBLS-35TLI TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/01/08 19 PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View 1 2 3 4 56 6 Bottom View φ b (48x) 5 4 3 2 1 A B C D D E F G H D1 e A B C D E F G H e E E1 A2 SEATING PLANE A1 A Notes: 1. Controlling dimensions are in millimeters. mBGA - 6mm x 8mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.24 0.60 7.90 5.90 mBGA - 8mm x 10mm INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETER Min. Typ. Max. 48 — 0.24 0.60 9.90 7.90 — — — — — 1.20 0.30 — 10.10 8.10 — INCHES Min. Typ. Max. Min. Typ. Max. 48 — — — — — 1.20 0.30 — 8.10 6.10 — 0.009 0.024 0.311 0.232 — — — — — 0.047 0.012 — 0.319 0.240 A A1 A2 D D1 E E1 e b — — — — — 0.047 0.012 — 0.398 0.319 0.009 0.024 0.390 0.311 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40 0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 E1 E Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 D N/2 SEATING PLANE ZD A . e b L A1 α C Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03