IS64WV25616EDBLL-10CTLA3

IS61WV25616EDBLL IS64WV25616EDBLL 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC FEATURES • High-speed access time: 8, 10 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby • Single power supply — Vdd 2.4V to 3.6V (10 ns) — Vdd 3.3V ± 10% (8 ns) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available • Error Detection and Error Correction JULY 2020 DESCRIPTION The ISSI IS61/64WV25616EDBLL is a high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61/64WV25616EDBLL is packaged in the JEDEC standard 44-pin TSOP-II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM Memory Lower IO Array256Kx8 A0-A17 Decoder 8 IO0-7 IO8-15 /CE /OE /WE /UB /LB 8 8 I/O Data Circuit 8 ECC ECC 12 12 8 ECC Array256K x4 4 Memory ECC Array256K x4 Upper IO Array256Kx8 8 4 Column I/O Control Circuit Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A2 07/14/2020 IS61/64WV25616EDBLL TRUTH TABLE Mode Not Selected Output Disabled Read Write I/O PIN WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vdd Current X H X X X High-Z High-Z Isb1, Isb2 H L H X X High-Z High-Z Icc X L X H H High-Z High-Z H L L L H Dout High-Z Icc H L L H L High-Z Dout H L L L L Dout Dout L L X L H Din High-Z Icc L L X H L High-Z Din L L X L L Din Din PIN CONFIGURATIONS 44-Pin TSOP (Type II) A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground *SOJ package under evaluation. 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 IS61/64WV25616EDBLL PIN CONFIGURATIONS 44-Pin LQFP* 48-Pin mini BGA (6mm x 8mm) 2 3 4 5 6 A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB 1 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC 2 3 A LB OE A0 A1 A2 N/C B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 1 *LQFP package under evaluation. PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. A2 07/14/2020 IS61/64WV25616EDBLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Vdd Vdd Relates to GND Tstg Storage Temperature Pt Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 6 pF 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. ERROR DETECTION AND ERROR CORRECTION • • • • Independent ECC for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) OPERATING RANGE (Vdd)1 Range Ambient Temperature Industrial –40°C to +85°C Automotive (A1) –40°C to +85°C Automotive (A3) –40°C to +125°C IS61WV25616EDBLL Vdd (8, 10ns) 2.4V-3.6V (10ns) 3.3V ± 10% (8ns) — — IS64WV25616EDBLL Vdd (10ns) — 2.4V-3.6V 2.4V-3.6V Note: 1. Contact SRAM@issi.com for 1.8V option 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 IS61/64WV25616EDBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 10% Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA Output LOW Voltage Vdd = Min., Iol = 8.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 2.4 — V — 0.4 V 2 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND ≤ Vin ≤ Vdd Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. Max. Unit 1.8 — V — 0.4 V 2.0 Vdd + 0.3 V –0.3 0.8 V –1 1 µA –1 1 µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. — 40 — 30 — 25 mA Supply Current Iout = 0 mA, f = fmax Ind. — 45 — 35 — 30 Auto. — — — 50 — 45 typ.(2) 21 21 Icc1 Operating Vdd = Max., Com. — 20 — 20 — 20 mA Supply Current Iout = 0 mA, f = 0 Ind. — 25 — 25 — 25 Auto. — — — 40 — 40 Isb1 TTL Standby Current Vdd = Max., Com. — 10 — 10 — 10 mA (TTL Inputs) Vin = Vih or Vil Ind. — 15 — 15 — 15 CE ≥ Vih, f = 0 Auto. — — — 30 — 30 Isb2 CMOS Standby Vdd = Max., Com. — 5 — 5 — 5 mA Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 6 — 6 — 6 Vin ≥ Vdd – 0.2V, or Auto. — — — 15 — 15 Vin ≤ 0.2V, f = 0 typ.(2) 1.5 1.5 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. A2 07/14/2020 2 3 4 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V 1 5 6 7 8 9 10 11 12 IS61/64WV25616EDBLL AC TEST CONDITIONS Parameter Unit (2.4V-3.6V) Input Pulse Level 0.4V to Vdd-0.3V Input Rise and Fall Times 1V/ ns Input and Output Timing Vdd/2 and Reference Level (VRef) Output Load See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 353 Ω 5 pF Including jig and scope Figure 2. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Min. Max. Min. Max. Min. Max. trc Read Cycle Time 8 — 10 — 20 — taa Address Access Time — 8 — 10 — 20 toha Output Hold Time 2.0 — 2.0 — 2.5 — tace CE Access Time — 8 — 10 — 20 tdoe OE Access Time — 4.5 — 4.5 — 8 OE to High-Z Output — 3 — 4 0 8 thzoe(2) (2) tlzoe OE to Low-Z Output 0 — 0 — 0 — thzce(2 CE to High-Z Output 0 3 0 4 0 8 tlzce(2) CE to Low-Z Output 3 — 3 — 3 — tba LB, UB Access Time — 5.5 — 6.5 — 8 thzb(2) LB, UB to High-Z Output 0 3 0 3 0 8 tlzb(2) LB, UB to Low-Z Output 0 — 0 — 0 — tpu Power Up Time 0 — 0 — 0 — tpd Power Down Time — 8 — 10 — 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 IS61/64WV25616EDBLL 1 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil) 2 t RC ADDRESS t OHA DOUT t AA 3 t OHA DATA VALID PREVIOUS DATA VALID READ1.eps 4 5 READ CYCLE NO. 2 (1,3) 6 tRC ADDRESS tAA tOHA 7 OE tHZOE tDOE tLZOE CE tACE tLZCE 8 tHZCE LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC 9 DATA VALID tPU 50% tPD 50% ICC ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. A2 07/14/2020 IS61/64WV25616EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 -10 -20 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time 8 — 10 — 20 — ns tsce CE to Write End 6.5 — 8 — 12 — ns taw Address Setup Time 6.5 — 8 — 12 — ns to Write End tha Address Hold from Write End 0 — 0 — 0 — ns tsa Address Setup Time 0 — 0 — 0 — ns tpwb LB, UB Valid to End of Write 6.5 — 8 — 12 — ns tpwe1 WE Pulse Width 6.5 — 8 — 12 — ns tpwe2 WE Pulse Width (OE = LOW) 8 — 10 — 17 — ns tsd Data Setup to Write End 5 — 6 — 9 — ns thd Data Hold from Write End 0 — 0 — 0 — ­ns thzwe(2) WE LOW to High-Z Output — 3.5 — 5 — 9 ns (2) tlzwe WE HIGH to Low-Z Output 2 — 2 — 3 — ns Notes: 1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 IS61/64WV25616EDBLL 1 AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) 2 t WC VALID ADDRESS ADDRESS t SA t SCE t HA 3 CE t AW t PWE1 t PWE2 WE 4 t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD 5 t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1.  WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2.  WRITE = (CE) [ (LB) = (UB) ] (WE). 6 7 8 WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS 9 VALID ADDRESS t HA OE CE 10 LOW t AW t PWE1 WE t SA t PWB 11 UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. A2 07/14/2020 12 IS61/64WV25616EDBLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PWB t PWB WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1.  The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2.  Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3.  WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 IS61/64WV25616EDBLL HIGH SPEED (IS61/64WV25616EDBLL) 1 DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 0.5 5 mA Ind. — — 6 Auto. 15 tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns trdr Recovery Time See Data Retention Waveform trc — — ns Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. 2 3 o 4 DATA RETENTION WAVEFORM (CE Controlled) 5 tSDR Data Retention Mode tRDR VDD 6 VDR 7 CE GND CE ≥ VDD - 0.2V 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A2 07/14/2020 IS61/64WV25616EDBLL ORDERING INFORMATION (HIGH SPEED) Industrial Range: -40°C to +85°C Speed (ns) 8 10 Order Part No. IS61WV25616EDBLL-8BLI IS61WV25616EDBLL-8TLI IS61WV25616EDBLL-10BLI IS61WV25616EDBLL-10TLI Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free Automotive (A1) Range: -40°C to +85°C Speed (ns) 10 Order Part No. Package IS64WV25616EDBLL-10BLA1 48 mini BGA (6mm x 8mm), Lead-free IS64WV25616EDBLL-10CTLA1 TSOP (Type II), Lead-free, Copper Leadframe Automotive (A3) Range: -40°C to +125°C Speed (ns) 10 12 Order Part No. Package IS64WV25616EDBLL-10BLA3 48 mini BGA (6mm x 8mm), Lead-free IS64WV25616EDBLL-10CTLA3 TSOP (Type II), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020 Rev. A2 07/14/2020 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61/64WV25616EDBLL Integrated Silicon Solution, Inc. — www.issi.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 Package Outline 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61/64WV25616EDBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A2 07/14/2020