IS64WV6416BLL
IS61WV6416BLL
®
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64K x 16 HIGH-SPEED CMOS STATIC RAM
APRIL 2019
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
The ISSI IS61/64WV6416BLL is a high-speed, 1,048,576-
High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
CMOS low power operation:
50 mW (typical) operating
25 µW (typical) standby
TTL compatible interface levels
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Automotive Temperature Available
Lead-free available
bit static RAM organized as 65,536 words by 16 bits.
It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as
fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low
power consumption.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64WV6416BLL is packaged in the JEDEC standard 44-pin TSOP-II, 44-pin 400-mil SOJ, and 48-pin mini
BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. C1
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IS64WV6416BLL
IS61WV6416BLL
®
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PIN CONFIGURATIONS
44-Pin TSOP-II
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
NC
A7
I/O3
VDD
E
VDD
I/O12
NC
NC
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
44-Pin SOJ (K)
PIN DESCRIPTIONS
A15
1
44
A0
A14
2
43
A1
A0-A15 Address Inputs
A13
3
42
A2
I/O0-I/O15
A12
4
41
OE
A11
5
40
UB
CE
6
39
LB
I/O0
7
38
I/O15
I/O1
8
37
I/O14
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O2
9
36
I/O13
LB
Lower-byte Control (I/O0-I/O7)
I/O3
10
35
I/O12
11
34
GND
UB
Upper-byte Control (I/O8-I/O15)
VDD
GND
12
33
VDD
I/O4
13
32
I/O11
I/O5
14
31
I/O10
I/O6
15
30
I/O9
I/O7
16
29
I/O8
WE
17
28
NC
A10
18
27
A3
A9
19
26
A4
A8
20
25
A5
A7
21
24
A6
NC
22
23
NC
NC
No Connection
Vdd Power
GND
2
Ground
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TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB UB
I/O0-I/O7 I/O8-I/O15 Vdd Current
Not Selected
X
H
X
X
X
High-Z
High-Z
Isb1, Isb2
Output Disabled
H
L
H
X
X
High-Z
High-Z
Icc
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
Dout
High-Z
Icc
H
L
L
H
L
High-Z
Dout
H
L
L
L
L Dout Dout
Write
L
L
X
L
H
Din
High-Z
Icc
L
L
X
H
L
High-Z
Din
L
L
X
L
L Din Din
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Vterm
Terminal Voltage with Respect to GND
Tstg
Storage Temperature
Pt
Power Dissipation
Vdd Vdd Related to GND
Value
Unit
–0.5 to Vdd+0.5 V
–65 to +150
°C
1.5
W
-0.2 to +3.9
V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE (Vdd)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
Vdd (15 ns)
2.5V-3.6V
2.5V-3.6V
2.5V-3.6V
Vdd (12 ns)
3.3V + 10%
3.3V + 10%
3.3V + 10%
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DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.5V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Note:
1.
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 1.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
2.3
—
V
—
0.4
V
2.0
Vdd + 0.3
V
–0.3
0.8
V
–2 2 µA
–2
2
µA
Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 10%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Note:
1.
4
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –4.0 mA
Vdd = Min., Iol = 8.0 mA
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
2.4
—
V
—
0.4
V
2
Vdd + 0.3
V
–0.3
0.8
V
–2 2 µA
–2
2
µA
Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested.
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®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
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-12 ns
-15 ns
Symbol Parameter
Test Conditions Options
Min. Max.
Min. Max.
Unit
Icc
Vdd Dynamic Operating Vdd = Max.,
c
om.
— 35 — 30 mA
Supply Current
Iout = 0 mA, f = fmax
ind.
— 45 — 40
auto
—
60
—
50
typ.(2)
— 20 — 20
Icc1
Operating Supply
Vdd = Max.,
com.
— 5 — 5 mA
Current
Iout = 0mA, f = 0 ind.
—
5 — 5
auto
— 5 — 5
Isb2
CMOS Standby
Vdd = Max.,
com.
— 20 — 20
uA
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
ind.
— 50 — 50
Vin ≥ Vdd – 0.2V, or
auto
—
75
—
75
Vin ≤ 0.2V, f = 0 typ.(2)
—
6
—
6
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd=2.5V, Ta=25oC. Not 100% tested.
CAPACITANCE(1)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
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AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
Unit
(2.5V-3.6V)
(3.3V + 10%)
0V to Vdd V
0V to Vdd V
1.5ns
1.5ns
Vdd/2 Vdd/2 + 0.05
See Figures 1a and 1b
See Figures 1a and 1b
AC TEST LOADS
319 Ω
Zo=50Ω
VRef
OUTPUT
30 pF
Including
jig and
scope
Figure 1a.
6
2.5V
50Ω
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 1b.
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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-12 ns
Symbol
Parameter Min. Max.
trc
Read Cycle Time
12
—
-15 ns
Min. Max. Unit
15 —
ns
taa
Address Access Time
—
12
—
15
ns
toha
Output Hold Time
3
—
3
—
ns
tace
CE Access Time
—
12
—
15
ns
OE Access Time
—
6
—
7
ns
tdoe
thzoe
OE to High-Z Output
—
6
0
6
ns
tlzoe(2)
OE to Low-Z Output
0
—
0
—
ns
thzce(2
CE to High-Z Output
0
6
0
6
ns
tlzce
CE to Low-Z Output
3
—
3
—
tba
LB, UB Access Time
—
6
—
7
ns
thzb
LB, UB to High-Z Output
0
6
0
6
ns
tlzb
LB, UB to Low-Z Output
0
—
0
—
ns
(2)
(2)
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0V to
Vdd V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = Vil, UB or LB = Vil)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CE
tACE
tHZCE
tBA
tHZB
tLZCE
LB, UB
DOUT
HIGH-Z
tLZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.
8
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
twc
Write Cycle Time
-12 ns
Min. Max.
12
—
-15 ns
Min. Max.
15
—
Unit
ns
tsce
CE to Write End
9
—
10
—
ns
taw
Address Setup Time
to Write End
9
—
10
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
LB, UB Valid to End of Write
9
—
10
—
ns
tpwe1
WE Pulse Width (OE = HIGH)
9
—
10
—
ns
tpwe2
WE Pulse Width (OE = LOW)
11
—
12
—
ns
tsd
Data Setup to Write End
9
—
9
—
ns
thd
Data Hold from Write End
0
—
0
—
ns
thzwe(3)
WE LOW to High-Z Output
—
6
—
7
ns
tlzwe
WE HIGH to Low-Z Output
3
—
3
—
ns
(3)
Notes:
1. Test conditions for IS61WV6416BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0V to Vdd V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
10
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WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
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WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
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DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Vdr Vdd for Data Retention
Test Condition
Operations Min.
See Data Retention Waveform
1.8
Idr
Vdd = 1.8V, CE ≥ Vdd – 0.2V
Data Retention Current
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note:
com.
ind.
auto
Typ.(1)
—
Max. Unit
3.6
V
—
6
20
µA
—
—
0
trc
6
6
—
—
50
75
—
ns
— ns
1. Typical values are measured at Vdd = 2.5V, Ta = 25oC. Not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE
GND
CE ≥ VDD - 0.2V
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ORDERING INFORMATION
Commercial Temperature Range: 0°C to +70°C
Speed (ns)
12
Order Part No.
IS61WV6416BLL-12KL
Package
400-mil Plastic SOJ, Lead-free
Industrial Temperature Range: –40°C to +85°C
Speed (ns)
12
12
12
12
12
15
15
15
Order Part No.
IS61WV6416BLL-12TI
IS61WV6416BLL-12TLI
IS61WV6416BLL-12KLI
IS61WV6416BLL-12BI
IS61WV6416BLL-12BLI
IS61WV6416BLL-15TLI
IS61WV6416BLL-15BI
IS61WV6416BLL-15BLI
Package
Plastic TSOP
Plastic TSOP, Lead-free
400-mil Plastic SOJ, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Temperature Range (A3): –40°C to +125°C
Speed (ns)
15 (121)
15 (121)
15 (121)
15 (121)
Order Part No.
IS64WV6416BLL-15TA3
IS64WV6416BLL-15TLA3
IS64WV6416BLL-15BA3
IS64WV6416BLL-15BLA3
Package
Plastic TSOP
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Note:
1. Speed = 12ns for Vdd = 3.3V + 10%. Speed = 15ns for Vdd = 2.5V- 3.6V.
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SEATING PLANE
NOTE :
1. Controlling dimension : mm
2. Dimension D and E1 do not include mold protrusion .
3. Dimension b2 does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.
12/19/2007
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IS64WV6416BLL
IS61WV6416BLL
IS64WV6416BLL
IS61WV6416BLL
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NOTE :
08/12/2008
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
Package Outline
16
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Θ
NOTE :
Θ
1. CONTROLLING DIMENSION : MM
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
06/04/2008
Rev. C1
04/01/2019
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
Package Outline
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IS64WV6416BLL
IS61WV6416BLL