IS65C51216AL

IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 45ns, 55ns • CMOS low power operation – 36 mW (typical) operating – 12 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply – 4.5V--5.5V Vdd • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Automotive temperature (-40oC to +125oC) • Lead-free available APRIL 2009 speed, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62C51216AL and IS65C51216AL are packaged in the JEDEC standard 48-pin mini BGA (9mm x 11mm) and 44-Pin TSOP (TYPE II). DESCRIPTION The ISSI IS62C51216AL and IS65C51216AL are high- FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 1 IS62C51216AL, IS65C51216AL PIN CONFIGURATIONS 48-Pin mini BGA (9mmx11mm) 1 2 3 4 5 6 PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CS1, CS2 OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground A B C D E F G H LB I/O8 I/O9 GND VDD I/O14 I/O15 A18 OE UB I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CS1 I/O1 I/O3 I/O4 I/O5 WE A11 CS2 I/O0 I/O2 VDD` GND I/O6 I/O7 NC 44-Pin TSOP (Type II) A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A8 A9 A10 A11 A17 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL TRUTH TABLE Mode Not Selected Output Disabled Read WE X X X H H H H H L L L CS1 H X X L L L L L L L L CS2 X L X H H H H H H H H OE X X X H H L L L X X X LB X X H L X L H L L H L UB X X H X L H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z dout High-Z High-Z dout dout dout dIn High-Z High-Z dIn dIn dIn Vdd Current Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Icc Icc Icc Write Icc OPERATING RANGE (Vdd) Range Ambient Temperature Vdd Speed Commercial Industrial Automotive 0°C to +70°C –40°C to +85°C –40°C to +125°C 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 45ns 55ns 55ns CAPACITANCE(1,2) Symbol cIn cout Parameter Input Capacitance Output Capacitance Conditions VIn = 0V Vout = 0V Max. 5 7 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°c, f = 1 MHz, Vdd = 5.0V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 3 IS62C51216AL, IS65C51216AL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm tstg Pt Iout Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VoH Output HIGH Voltage VoL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage(1) ILI Input Leakage Test Conditions Vdd = Min., IoH = –1 mA Vdd = Min., IoL = 2.1 mA GND ≤ VIn ≤ Vdd Com. Ind. Auto. Com. Ind. Auto. Min. 2.4 — 2.2 –0.3 –1 –2 –5 –1 –2 –5 Max. — 0.4 Vdd + 0.5 0.8 1 2 5 1 2 5 Unit V V V V µA ILo Output Leakage GND ≤ Vout ≤ Vdd Outputs Disabled µA Note: 1. VIL (min) = -0.3V DC; VIL (min) = -2.0V AC (pulse width -2.0 ns). Not 100% tested. VIH (max) = Vdd + 0.3V DC; VIH (max) = Vdd + 2.0V AC (pulse width -2.0 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 481 Ω 5V OUTPUT 30 pF Including jig and scope 255 Ω 5V OUTPUT 5 pF Including jig and scope 255 Ω 481 Ω Figure 1 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 5 IS62C51216AL, IS65C51216AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., CE = VIL Supply Current Iout = 0 mA, f = fmaX VIn = VIH or VIL Icc1 CE = VIL, VIn = VIH or VIL, I I/o= 0 mA TTL Standby Current Vdd = Max., (TTL Inputs) VIn = VIH or VIL, CE ≥ VIH, f = 0 CMOS Standby Vdd = Max., Current (CMOS Inputs) CE ≥ Vdd – 0.2V, VIn ≥ Vdd – 0.2V, or VIn ≤ Vss + 0.2V, f = 0 Average operating Current -45 ns Min. Max. — 25 13 — 10 — 1 — 40 15 -55 ns Min. Max. — — 12 mA — — — — — — 10 20 mA 1.5 2 µA 60 180 25 40 Unit mA Isb1 Isb2 Com. Ind. Auto. typ.(2) Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. typ.(2) Note: 1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical Values are measured at Vcc = 5V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toHa3 Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output LB, UB Access Time 45 ns Min. 45 — 10 — — — 5 0 10 — 0 0 Max. — 45 — 45 20 15 — 15 — 45 15 — 55 ns Min. 55 — 10 — — — 5 0 10 — 0 0 Max. — 55 — 55 25 20 — 20 — 55 20 — 70 ns Min. 70 — 10 — — — 5 0 10 — 0 0 Max. — 70 — 70 35 25 — 25 — 70 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns tacs1/tacs2 tdoe tHzoe(2) tLzoe(2) tHzcs1/tHzcs2(2) tLzcs1/tLzcs2(2) tba tHzb LB, UB to High-Z Output tLzb LB, UB to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. 10ns for CMOS Loading. 8ns @ AC Loading. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cs2 = WE = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DATA VALID DQ0-D15 PREVIOUS DATA VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 7 IS62C51216AL, IS65C51216AL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CS1s tACE1/tACE2 tLZOE CS2s tLZCE1/ tLZCE2 tHZCS1/ tHZCS1 LBs, UBs tLZB tBA tHZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = VIL. cs2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc Parameter Write Cycle Time CS1/CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output 45ns Min. Max. 45 — 35 — 35 — 0 — 0 — 35 — 35 — 25 — 0 — — 20 5 — 55 ns Min. Max. 55 — 45 — 45 — 0 — 0 — 45 — 40 — 30 — 0 — — 20 5 — 70 ns Min. Max. 70 — 60 — 60 — 0 — 0 — 60 — 50 — 30 — 0 — — 30 5 — Unit ns ns ns ns ns ns ns ns n s ns ns tscs1/tscs2 taw tHa tsa tPwb tPwe(4) tsd tHd tHzwe(3) tLzwe(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. tPwe > tHzwe + tsd when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE WE LB, UB tSA tHZWE tPWB tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 9 IS62C51216AL, IS65C51216AL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS ADDRESS 1 t WC ADDRESS 2 OE t SA CS1 CS2 LOW HIGH WE t HA t SA t PBW t PBW WORD 2 t HA UB, LB WORD 1 t HZWE DOUT DATA UNDEFINED HIGH-Z t LZWE t HD DATAIN VALID t SD DIN t SD DATAIN VALID t HD UB_CSWR4.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 11 IS62C51216AL, IS65C51216AL DATA RETENTION SWITCHING CHARACTERISTICS (4.5V - 5.5V) Symbol Vdr Idr Parameter Vdd for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vdd = 2.0V, CS1 ≥ Vdd – 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Auto. Min. 2.0 — — — — 0 trc Typ.(1) 15 — — Max. 5.5 20 40 60 180 — — Unit V µA ns ns tsdr trdr Note: 1. Typical Values are measured at Vcc = 5V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CS1 Controlled) tSDR VDD 1.65V Data Retention Mode tRDR 1.4V VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CE2 2.2V VDR 0.4V GND CS2 ≤ 0.2V tSDR tRDR 3.0 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL IS62C51216AL (4.5V - 5.5V) Industrial Range: –40°C to +85°C Speed (ns) 55 Order Part No.* IS62C51216AL-55TLI IS62C51216AL-55MLI Package TSOP-II, Lead-free mini BGA, Lead-free (9mmx11mm) *Devices will meet 45ns when used in 0oC to +70oC temperature range. IS65C51216AL (4.5V - 5.5V) Industrial Range: –40°C to +125°C Speed (ns) 55 Order Part No. IS65C51216AL-55CTLA3 IS65C51216AL-55MLA3 Package TSOP-II, Lead-free, Copper Lead-frame mini BGA, Lead-free (9mmx11mm) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 13 14 Θ IS62C51216AL, IS65C51216AL NOTE : 1. CONTROLLING DIMENSION : MM 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. Θ Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Package Outline 06/04/2008 Rev. A 03/18/09 IS62C51216AL, IS65C51216AL 08/21/2008 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 03/18/09 NOTE : 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 15