IS66WV51216EBLL-70TLI

IS66WV51216EALL IS66/67WV51216EBLL SEPTEMBER 2022 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM DESCRIPTION Features  High-Speed access time : - 70ns ( IS66WV51216EALL ) - 60ns (IS66/67WV51216EBLL )  CMOS Lower Power Operation  Single Power Supply - VDD =1.7V~1.95V( IS66WV51216EALL ) - VDD =2.5V~3.6V (IS66/67WV51216EBLL )  Three State Outputs  Data Control for Upper and Lower bytes  Lead-free Available FUNCTIONAL BLOCK DIAGRAM The ISSI IS66WV51216EALL and IS66/67WV51216EBLL are high-speed,8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI’s high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The IS66WV51216 EALL and IS66/67WV51216EBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm) and 44-Pin TSOP(TYPE-II). The device is also available for die sales. Address Decode Logic A0~A18 512K X 16 DRAM Memory Array VDD GND I/O0-I/O7 Lower Byte I/O DATA CIRCUIT I/O8-I/O15 COLUMN I/O Upper Byte CS2 CS1# OE# WE# UB# LB# Control Logic Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu mes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specificatio n before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 1 IS66WV51216EALL IS66/67WV51216EBLL PIN CONFIGURATIONS 48-Ball miniBGA (6mm x 8mm) Ball Assignment 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B I/Q8 UB# A3 A4 CS1# I/Q0 C I/Q9 I/Q10 A5 A6 I/Q1 IQ2 D GND IQ11 A17 A7 I/Q3 VDD E VDD IQ12 NC A16 I/Q4 GND F I/Q14 I/Q13 A14 A15 I/Q5 I/Q6 G I/Q15 NC A12 A13 WE# I/Q7 H A18 A8 A9 A10 A11 NC 44-pin TSOP (Type II) A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE# A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A8 A9 A10 A11 A17 PIN DESCRIPTIONS Symbol Type A0~A18 Input I/Q0~I/Q15 Input / Output CS1#, CS2 Input Chip Enable OE# Input Output Enable WE# Input Write Enable UB# Input Upper Byte select LB# Input Lower Byte select VDD Power Supply Power GND Power Supply Ground Rev. B1 | 09/14/2022 Description Address Inputs Data Inputs/Outputs www.issi.com - SRAM@issi.com 2 IS66WV51216EALL IS66/67WV51216EBLL POWER UP INITIALIZATION IS66WV51216EALL and IS66/67WV51216EBLL include an on-chip voltage sensor used to launch the power-up initialization process. When VDD reaches a stable level at or above the VDD (min) the device will require 50μs to complete its self-initialization process. During the initialization period, CS1# should remain HIGH. When initializeation is complete, the device is ready for normal operation. 50 us VDD( min) Device Initialization VDD 0V Device for Normal Operation TRUTH TABLE Mode WE# CS1# CS2 OE# LB# UB# I/O0 – I/O7 I/O8 – I/O15 Not Selected X X H X X L X X X X H X High-Z High-Z High-Z High-Z ISB1,ISB2 Output Disabled H H L L H H H H L X X L High-Z High-Z High-Z High-Z ICC ICC Read H H H L L L H H H L L L L H L H L L DOUT High-Z High-Z DOUT D DOUT ICC ICC ICC Write L L L L L L H H H X X X L H L H L L Din High-Z Din High-Z Din Din ICC ICC ICC Notes: VDD Current ISB1,ISB2 OUT CS2 input signal pin is only available for 48-ball mini BGA package part. CS2 input is internally enabled for 44-pin TSOP II package part. OPERATING RANGE (VDD) Range Ambient Temperature IS66WV51216EALL (70ns) IS66WV51216EBLL (55ns, 70ns) IS66WV51216EBLL (55ns, 70ns) Industrial –40°C to +85°C 1.7V – 1.95V 2.5V – 3.6V – Automotive , A1 –40°C to +85°C – – 2.5V – 3.6V Automotive , A2 –40°C to +105°C – – 2.5V – 3.6V Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 3 IS66WV51216EALL IS66/67WV51216EBLL ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit -0.2 to VDD + 0.3 V -40 to +85 °C VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under BIAS VDD VDD Related to GND -0.2 to +3.8 V TSTG Storage Temperature -65 to +150 °C PT Power Dissipation 1.0 W Notes: Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.5V-3.6V (IS66/67WV51216EBLL) Symbol Parameter Test Conditions VDD Min. Max. Unit VOH VOL Output HIGH Voltage Output LOW Voltage IoH = -1 mA IoL = 2.1 mA 2.5-3.6V 2.5-3.6V 2.2 — — 0.4 V V VIH Input HIGH Voltage(1) 2.5-3.6V 2.2 VDD + 0.3 V VIL Input LOW Voltage(1) 2.5-3.6V –0.2 0.6 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 μA ILo Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 μA Notes: 1. VILL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max.) = VDD + 2.0V AC (pulse width < 10ns). Not 100% test DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.7V-1.95V(IS66WV51216EALL) Symbol Parameter Test Conditions VDD Min. Max . Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.7-1.95V 1.4 — V VOL VIH Output LOw Voltage Input HIGH Voltage(1) IOL = 0.1 mA 1.7-1.95V 1.7-1.95V — 1.4 0.2 VDD + 0.2 V V VIL Input LOw Voltage(1) 1.7-1.95V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 μA ILo Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 μA Notes: 1. VILL (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max.) = VDD + 1.0V AC (pulse width < 10ns). Not 100% test Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 4 IS66WV51216EALL IS66/67WV51216EBLL CAPACITANCE Symbol Description Conditions MIN MAX Unit CIN Input Capacitance VIN = 0V - 8 pF CIO Input/Output Capacitance (DQ) Vout = 0V - 10 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 1.7V – 1.95V ( Unit ) 2.5V – 3.6V ( Unit ) Input Pulse Level 0.4V to VDD – 0.2V 0.4V to VDD – 0.3V Input Rise and Fall Time 5ns 5ns Input and Output Timing and Reference Level VREF VREF Output Load See Figures 1 and 2 See Figures 1 and 2 Symbol 1.7V – 1.95V 2.5V – 3.6V R1(Ω) 3070 1029 R2(Ω) 3150 1728 VREF 0.9V 1.4V VTM 1.8V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including Jig and scope Figure 1 Rev. B1 | 09/14/2022 R2 5 pF Including Jig and scope R2 Figure 2 www.issi.com - SRAM@issi.com 5 IS66WV51216EALL IS66/67WV51216EBLL 1.7V-1.95V POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC ICC1 Parameter Conditions Device TYP. MAX. 70ns Unit VDD Dynamic Operating Supply Current VDD=Max.,IOUT=0mA, f=fMAX , All inputs = 0.4V or VDD – 0.2V Com. Ind. Auto - 20 25 30 mA Operating Supply Current VDD=Max.,CS1#=0.2V, WE#= VDD – 0.2V, f=1MHz Com. Ind. Auto - 8 8 10 mA VDD=Max.,VIN=VIH or VIL, CS1# = VIH, CS2=VIL , Com. Ind. Auto - 0.6 0.6 1 mA Com. Ind. Auto - 100 120 150 uA ISB1 TTL Standby Current ( TTL Inputs ) ISB2 CMOS Standby Current ( CMOS Inputs ) f=1MHz VDD=Max., CS1# > VDD – 0.2V, CS2 < 0.2V, VIN > VDD – 0.2V or VIN < 0.2V, f=0 Notes: 1. At f = f MAX , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change. 2.5V-3.6V POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC ICC1 ISB1 ISB2 Parameter Conditions Device TYP MAX 55ns Unit VDD Dynamic Operating Supply Current VDD=Max.,IOUT=0mA, f=fMAX , All inputs = 0.4V or VDD – 0.3V Com. Ind. Auto A2 Typ.(2) - 25 28 35 15 mA Operating Supply Current VDD=Max.,CS1#=0.2V, WE#= VDD – 0.2V, f=1MHz Com. Ind. Auto A2 - 8 8 10 mA VDD=Max.,VIN=VIH or VIL, CS1# = VIH, CS2=VIL , f=1MHz Com. Ind. Auto A2 - 0.6 0.6 1 mA VDD=Max., CS1# > VDD – 0.2V, CS2 < 0.2V, VIN > VDD – 0.2V or VIN < 0.2V ,f=0 Com. Ind. Auto A2 Typ.(2) - 100 130 150 75 uA TTL Standby Current ( TTL Inputs ) CMOS Standby Current ( CMOS Inputs ) Notes: 1. At f =fMAX , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, Ta = 25 ºC , and not 100% tested. Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 6 IS66WV51216EALL IS66/67WV51216EBLL READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range) Symbol -55 Parameter -70 Unit Notes Min Max Min Max 60 - 70 - ns - 60 - 70 ns 10 - 10 - ns CS1#/CS2 Acess Time - 60 - 70 ns tDOE OE# Access Time - 25 - 35 ns 1 tHZOE OE# to High-Z output - 20 - 25 ns 2 tLZOE OE# to Low-Z output 5 - 5 - ns 2 tCSM Maximum CS1#/CS2 pulse width - 15 - 15 us tHZCS1/HZCS2 CS1#/CS2 to High-Z output 0 20 0 25 ns 2 tLZCS1/HZCS2 CS1#/CS2 to Low-Z output 10 - 10 - ns 2 tRC Read cycle time tAA Address Acess Time tOHA Output Hold Time tACS1/ACS2 1 tBA UB#/LB# Acess Time - 60 - 70 ns 1 tHZB UB#/LB# to High-Z output 0 20 0 25 ns 2 tLZB UB#/LB# to Low-Z output 0 - 0 - ns 2 tCPH CS1# HIGH (CS2 LOW) time 5 - 5 - ns Notes: 1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5. 2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1) (Address Controlled, OE#= VIL, WE#=VIH, UB# or LB# = VIL) tRC Address tCSM CS1# CS2 tAA tOHA DQ 0-15 PREVIOUS DATA VALID tOHA DATA VALID Notes: 1. WE# is HIGH for a Read Cycle. Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 7 IS66WV51216EALL IS66/67WV51216EBLL READ CYCLE NO. 2(1) (CS1#, CS2, OE# and UB#/LB# Controlled) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tCSM CS1# tLZOE tACE1/tACE2 CS2 tLZCS1/ tLZCS2 tHZCS1/ tHZCS2 tCSM UB#,LB# tLZB DOUT HIGH-Z tBA tHZB DATA VALID Notes: 1. Address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with CS1# HI GH (CS2 LOW) transition. Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 8 IS66WV51216EALL IS66/67WV51216EBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol tWC tSCS1/SCS2 -55 Parameter -70 Unit Min Max Min Max Write Cycle Time 55 - 70 - ns CS1#/CS2 to Write End 45 - 60 - ns - 15 - 15 us tCSM Maximum CS1#/CS2 pulse width tAW Address Setup to Write Time 45 - 60 - ns tHA Address Hold to End of Write 0 - 0 - ns tSA Address Setup Time 0 - 0 - ns tPWB UB#/LB# Valid to End of Write 45 - 60 - ns tPWE WE# Pulse Width 45 - 60 - ns tSD Data Setup Time 25 - 30 - ns Notes tHZWE WE# LOW to High-Z output - 20 - 30 ns 3 tLZWE WE# HIGH to Low-Z output 5 - 5 - ns 3 tCPH CS1# HIGH (CS2 LOW) time 5 - 5 - ns Notes: 1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5. 2. The internal write time is defined by the overlap of CS1#, UB#, LB# and WE# LOW, CS2 HIGH . All signals must be in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signals that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. 4. tPWE > tHzWE + tSD when OE# is LOW. 5. Chip Select Active Time (both CS1# LOW and CS2 HIGH) must not be longer than tCMS of 15 us. Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 9 IS66WV51216EALL IS66/67WV51216EBLL AC WAVEFORMS WRITE CYCLE NO. 1(1) (CS1# Controlled, OE#= HIGH or LOW) tWC ADDRESS tHA CS1# tCSM CS2 tAW tPWE WE# tPWB UB#,LB# tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD tHD DATA- IN VALID DIN Notes: 1. Write address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with C S1# HIGH (CS2 LOW) transition. WRITE CYCLE NO. 2 (WE# Controlled, OE#= HIGH during Write Cycle) tWC ADDRESS OE# tSCS1 tHA CS1# tSCS2 CS2 tAW WE# tPWE UB#,LB# tHZWE tSA DOUT DIN Rev. B1 | 09/14/2022 DATA UNDEFINED HIGH-Z tSD tLZWE tHD DATA -IN VALID www.issi.com - SRAM@issi.com 10 IS66WV51216EALL IS66/67WV51216EBLL WRITE CYCLE NO. 3 (WE# Controlled, OE#= LOW during Write Cycle) tWC ADDRESS LOW OE# tHA tSCS1 CS1# tSCS2 CS2 tAW WE# tPWE tPWB UB#,LB# tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD tHD DATA-IN VALID DIN WRITE CYCLE NO. 4 (UB# / LB# Controlled, CS2 is HIGH during Write Cycle) tWC ADDRESS tWC ADDRESS 1 ADDRESS 2 tCSM CS1# tSA tHA tHA tSA WE# UB#,LB# tHZWE DOUT DATA UNDEFINED DIN Rev. B1 | 09/14/2022 tPWB tPWB WORD 1 WORD 2 tLZWE HIGH-Z tSD tHD DATA IN VALID www.issi.com - SRAM@issi.com DATA IN VALID 11 IS66WV51216EALL IS66/67WV51216EBLL AVOIDABLE TIMING and RECOMMENDATIONS Figure 3a : tCSM Violation 15us CS1# WE# Address Figure 3b : Recommendation 15us CS1# 15 us 5ns WE# Address Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 12 IS66WV51216EALL IS66/67WV51216EBLL AVOIDABLE TIMING and RECOMMENDATIONS Figure 4a : tCSM Violation CS1#,WE# UB# &LB# 15us Address Figure 4b : Recommendation 15us WE# , UB# , LB# 15us CS1# Address Notes: 1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH action is performed only when the device is not selected (Chip Select Pins are Disabled). A hidden REFRESH action has to be executed by the device at least once every 15 μs of tCSM. 2. Figure 3a shows a timing example in which consecutive READ cycles for more than 15 us . This timing should be avoided for proper REFRESH operation. REFRESH operation can begin only during Chip Select pins are Disabled (CS1# is High and CS2 is Low ) for more than 5ns. Example on how to avoid tCSM violation in Figure 3a is shown in Figure 3b. 3. Figure 4a shows a timing example in which a single WRITE operation is maintained for a period greater than 15 μs. Since a proper REFRESH action cannot be performed during device is selected by Chip Select pins, information stored in the device will not be retained if this timing occurs. Figure 4b is a timing example of using CS1# signal toggling for proper the WRITE operation Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 13 IS66WV51216EALL IS66/67WV51216EBLL IS66WV51216EALL Industrial Temperature Range: (-40oC to +85oC) Voltage Range : 1.7V to 1.95V Config. Speed (ns) 512K x16 70 Order Part No. Package IS66WV51216EALL-70TLI IS66WV51216EALL-70BLI TSOP-II, Lead-free mini BGA(6mm x 8mm), Lead-free IS66WV51216EBLL Industrial Temperature Range: (-40oC to +85oC) Voltage Range : 2.5V to 3.6V Config. Speed (ns) Order Part No. Package 512K x16 55 IS66WV51216EBLL-55TLI IS66WV51216EBLL-55BLI TSOP-II, Lead-free mini BGA(6mm x 8mm), Lead-free 70 IS66WV51216EBLL-70TLI IS66WV51216EBLL-70BLI TSOP-II, Lead-free mini BGA(6mm x 8mm), Lead-free IS67WV51216EBLL Automotive (A1) Temperature Range: (-40oC to +85oC) Voltage Range : 2.5V to 3.6V Config. Speed (ns) Order Part No. Package 512K x16 55 IS67WV51216EBLL-55TLA1 IS67WV51216EBLL-55BLA1 TSOP-II, Lead-free mini BGA(6mm x 8mm), Lead-free 70 IS67WV51216EBLL-70TLA1 IS67WV51216EBLL-70BLA1 TSOP-II, Lead-free mini BGA(6mm x 8mm), Lead-free Notes : 1. Please contact ISSI SRAM marketing at sram@issi.com if you need -40 oC to +105 oC product. Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 14 IS66WV51216EALL IS66/67WV51216EBLL Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 15 IS66WV51216EALL IS66/67WV51216EBLL Rev. B1 | 09/14/2022 www.issi.com - SRAM@issi.com 16