IS93C66A-3GRI

IS93C56A IS93C66A ISSI MAY 2006 ® 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM FEATURES • Industry-standard Microwire Interface — Non-volatile data storage — Wide voltage operation: Vcc = 1.8V to 5.5V — Auto increment for efficient data dump • User Configured Memory Organization — By 16-bit or by 8-bit • Hardware and software write protection — Defaults to write-disabled state at power-up — Software instructions for write-enable/disable • Enhanced low voltage CMOS E2PROM technology • Versatile, easy-to-use Interface — Self-timed programming cycle — Automatic erase-before-write — Programming status indicator — Word and chip erasable — Chip select enables power savings • Durable and reliable — 40-year data retention after 1M write cycles — 1 million write cycles — Unlimited read cycles — Schmitt-trigger inputs • Industrial and Automotive Temperature Grade • Lead-free available DESCRIPTION The IS93C56A/66A are 2kb/4kb non-volatile, ISSI ® serial EEPROMs. They are fabricated using an enhanced CMOS design and process. The IS93C56A/66A contain power-efficient read/write memory, and organization of either 256/512 bytes of 8 bits or 128/256 words of 16 bits. When the ORG pin is connected to Vcc or left unconnected, x16 is selected; when it is connected to ground, x8 is selected. The IS93C56A/66A are fully backward compatible with IS93C56/66. An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the devices are write-enabled. A selected x8 byte or x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program an entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/ BUSY status by raising chip select (CS). The selftimed write cycle includes an automatic erasebefore-write capability. The devices can output any number of consecutive bytes/words using a single READ instruction. FUNCTIONAL BLOCK DIAGRAM DUMMY BIT R/W AMPS INSTRUCTION DECODE, CONTROL, AND CLOCK GENERATION ADDRESS REGISTER ADDRESS DECODER EEPROM ARRAY 256/512x8 128/256x16 DATA REGISTER DIN INSTRUCTION REGISTER DOUT CS SK WRITE ENABLE HIGH VOLTAGE GENERATOR Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 05/02/06 1 IS93C56A IS93C66A ISSI 8-Pin JEDEC SOIC “GR” ® PIN CONFIGURATIONS 8-Pin DIP, 8-Pin TSSOP CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC ORG GND CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC ORG GND PIN DESCRIPTIONS CS SK DIN DOUT ORG NC Vcc GND Chip Select Serial Data Clock Serial Data Input Serial Data Output Organization Select Not Connected Power Ground instruction begins with a start bit of the logical “1” or HIGH. Following this are the opcode (2 bits), address field (8 or 9 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway. Read (READ) The READ instruction is the only instruction that outputs serial data on the DOUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical “0” bit precedes the actual 8 or 16-bit output data string.) The output on DOUT changes during the low-to-high transitions of SK (see Figure 3). Applications The IS93C56A/66A are very popular in many applications which require low-power, low-density storage. Applications using these devices include industrial controls, networking, and numerous other consumer electronics. Low Voltage Read The IS93C56A/66A are designed to ensure that data read operations are reliable in low voltage environments. They provide accurate operation with Vcc as low as 1.8V. Endurance and Data Retention The IS93C56A/66A are designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). They provide 40 years of secure data retention without power after the execution of 1M programming cycles. Auto Increment Read Operations In the interest of memory transfer operation applications, the IS93C56A/66A are designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8 or 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead. Device Operations The IS93C56A/66A are controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 05/02/06 IS93C56A IS93C66A ISSI Write All (WRALL) ® Write Enable (WEN) The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.) The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 200 ns (tCS), the DOUT pin indicates the READY/BUSY status of the chip (see Figure 6). Vcc is required to be above 4.5V for WRALL to function properly. Write Disable (WDS) The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. Write (WRITE) The WRITE instruction includes 8 or 16 bits of data to be written into the specified register. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is writeenabled, then the falling edge of CS initiates the selftimed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 200 ns (5V operation) after the falling edge of CS (tCS) DOUT will indicate the READY/BUSY status of the chip. Logical “0” means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/ BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle, tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag. Erase Register (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/BUSY status of the chip: a logical “0” indicates programming is still in progress; a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8). Erase All (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9). Vcc is required to be above 4.5V for ERALL to function properly. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 05/02/06 3 IS93C56A IS93C66A ISSI 8-bit Organization (ORG = GND) Address (1) Input Data x(A7-A0) 11xxxxxxx x(A7-A0) 01xxxxxxx 00xxxxxxx x(A7-A0) 10xxxxxxx — — (D7-D0) (D7-D0) — — — ® INSTRUCTION SET - IS93C56A (2kb) 16-bit Organization (ORG = Vcc) Address ( 1) Input Data x(A6-A0) 11xxxxxx x(A6-A0) 01xxxxxx 00xxxxxx x(A6-A0) 10xxxxxx — — (D15-D0) (D15-D0) — — — Instruction (2) READ WEN (Write Enable) WRITE Start Bit OP Code 1 1 1 1 1 1 1 10 00 01 00 00 11 00 WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers) Notes: 1. x = Don't care bit. 2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored, and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted. INSTRUCTION SET - IS93C66A (4kb) 8-bit Organization (ORG = GND) Address (1) Input Data (A8-A0) 11xxxxxxx (A8-A0) 01xxxxxxx 00xxxxxxx (A8-A0) 10xxxxxxx — — (D7-D0) (D7-D0) — — — 16-bit Organization (ORG = Vcc) Address ( 1) Input Data (A7-A0) 11xxxxxx (A7-A0) 01xxxxxx 00xxxxxx (A7-A0) 10xxxxxx — — (D15-D0) (D15-D0) — — — Instruction (2) READ WEN (Write Enable) WRITE Start Bit OP Code 1 1 1 1 1 1 1 10 00 01 00 00 11 00 WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers) Notes: 1. x = Don't care bit. 2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored, and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 05/02/06 IS93C56A IS93C66A ISSI Value –0.5 to +6.5 –0.5 to Vcc + 0.5 –55 to +125 –65 to +150 5 Unit V V °C °C mA ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (IS93C56A-2, IS93C66A-2) Range Industrial Ambient Temperature –40°C to +85°C VCC 1.8V to 5.5V Note: ISSI offers Industrial grade for Commercial applications (0oC to +70oC) OPERATING RANGE (IS93C56A-3, IS93C66A-3) Range Automotive Ambient Temperature –40°C to +125°C VCC 2.5V to 5.5V CAPACITANCE Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 5 Unit pF pF Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 05/02/06 5 IS93C56A IS93C66A ISSI Test Conditions IOL = 100 µA IOL = 2.1mA IOH = –100 µA IOH = –400 µA Vcc 1.8V to 2.7V 2.7V to 5.5V 1.8V to 2.7V 2.7V to 5.5V 1.8V to 5.5V 1.8V to 5.5V VIN = 0V to VCC (CS, SK,DIN,ORG) VOUT = 0V to VCC, CS = 0V Min. — — VCC – 0.2 2.4 0.7XVCC –0.3 0 0 Max. 0.2 0.4 — — VCC+1 0.2XVCC 2.5 2.5 ® DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C for Industrial and –40°C to +125°C for Automotive. Symbol VOL2 VOL1 VOH2 VOH1 VIH VIL ILI ILO Notes: Automotive grade devices in this table are tested with Vcc = 2.5V to 5.5V. An operation with Vcc