IT6251FN/AX

廖 R 19 ， 51 8 71 44 58 5 QQ : IT6251 34 1 LVDS to DispalyPort 1.1a Transmitter Te l: 18 66 4 Preliminary Datasheet ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Specification V0.2 www.ite.com.tw Jul-2010 Rev:0.2 1/8 IT6251 General Description 71 44 51 8 19 ， 廖 R The IT6251 is a high-performance single-chip De-SSC LVDS to DisplayPort converter. Combined with LVDS receiver and DisplayPort Transmitter, the IT6251 supports LVDS input and DisplayPort 1.1a output by conversion function. The build-in LVDS receiver can support single-link and dual-link LVDS inputs, and the build-in DisplayPort transmitter is fully compliant with DisplayPort 1.1a specification. With high speed LVDS RX, the IT6251 can support resolution up to 1080P and UXGA and 10-bit deep colors. 34 1 58 5 QQ : In order to reduce the EMI noise on legacy system application, the traditional LVDS source will transmit differential signals with spread spectrum, but this spread spectrum does not be allowed for DisplayPort protocol. The IT6251 also build-in unique De-SSC ( De-Spread Spectrum ) function , it can help customers easily to adopt the IT6251 on the EMI-concerned platform, with SSC has been generated from LVDS source processors. 66 4 Features ( LVDS RX ) 18 • Support LVDS Input modes: Single Link, Dual Link Te • Support input color depth up to 10bit l: • Support input clock rate up to 165MHz 司 ， • Support De-SSC ( De-Spread Spectrum ) 限 公 • Support Data Mapping: Open LDI / JEIDA , VESA 深 讯 科 合 圳



DisplayPort 1.1a transmitter Compliant with DisplayPort 1.1a Supporting two link speeds, HBR(2.7Gbps) and RBR(1.62Gbps). Various video input interface supporting digital video standards such as:  18/24/30/36-bit RGB4:4:4 Software programmable DispalyPort output swing and pre-emphasis level Embedded full-function pattern generator MCCS over AUX channel Intelligent, programmable power management 市 金



技 有 Features (DisplayPort TX) www.ite.com.tw Jul-2010 Rev:0.2 2/8 IT6251 Features ( Combined ) 廖 R • Support up to Full-HD/1080P , and WQXGA(2560x1600 RB) display format 19 ， • Support deep color depth up to 10bit • 64-pin QFN (9mm x 9mm) package 71 44 51 8 • RoHS Compliant ( 100% Green available ) Temperature Range Package Type IT6251 0~70 64-pin QFN Green/Pb free Option Green 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 Model QQ : Ordering Information www.ite.com.tw Jul-2010 Rev:0.2 3/8 www.ite.com.tw PVCC0 PVCC1 REXT AVCC18 TX0P TX0N AVCC18 TX1P TX1N AVCC18 TX2P TX2N AVCC18 TX3P l: Te ， 司 公 限 技 TX3N有 AVCC18 讯 科 合 市 金 圳 深 58 5 34 1 66 4 18 QQ : 71 44 51 8 19 ， 廖 R RXNA1 RXPA1 RXNB1 RXPB1 AVCC RXNC1 RXPC1 RXNCLK RXPCLK ANVDD RXND1 RXPD1 RXNE1 RXPE1 APVDD IVDD IT6251 Pin Diagram Figure 1. IT6251 pin diagram Jul-2010 Rev:0.2 4/8 IT6251 Pin Description Direction Description Type RXNA1 Analog LVDS first link negative input LVDS RXPA1 Analog LVDS first link positive input LVDS RXNB1 Analog LVDS first link negative input LVDS 19 RXPB1 Analog LVDS first link positive input LVDS RXNC1 Analog LVDS first link negative input 51 8 20 LVDS 22 RXPC1 Analog LVDS first link positive input LVDS 23 RXND1 Analog LVDS first link negative input LVDS 27 RXPD1 Analog LVDS first link positive input LVDS 28 RXNE1 Analog LVDS first link negative input LVDS 29 RXPE1 Analog LVDS first link positive input LVDS 30 RXNCLK Analog LVDS negative clock input LVDS 24 RXPCLK Analog LVDS positive clock input LVDS 25 RXNA2 Analog LVDS second link negative input LVDS 34 RXPA2 Analog LVDS second link positive input LVDS 35 RXNB2 Analog LVDS second link negative input LVDS 36 RXPB2 Analog LVDS second link positive input LVDS 37 RXNC2 Analog LVDS second link negative input LVDS 39 RXPC2 Analog LVDS second link positive input LVDS 40 RXND2 Analog LVDS second link negative input LVDS 42 RXPD2 Analog LVDS second link positive input LVDS 43 RXNE2 Analog LVDS second link negative input LVDS 44 RXPE2 Analog LVDS second link positive input LVDS 45 Direction Description Type Pin No. Input Hardware reset pin. Active LOW (5V-tolerant) LVTTL 7 PCSCL Input Serial Programming Clock for chip programming (5V-tolerant) LVTTL 14 PCSDA I/O Serial Programming Data for chip programming (5V-tolerant) LVTTL 15 PCADR Input Serial programming device address select LVTTL 13 HPD Input Hot Plug Detection (5V-tolerant) LVTTL 5 17 19 ， 18 71 44 QQ : 58 5 34 1 66 4 18 l: Te ， 司 公 限 技 有 讯 科 Pin No. 廖 R Pin Name 圳 LVDS front-end interface pins Pin Name 深 市 金 SYSRSTN 合 Programming Pins www.ite.com.tw Jul-2010 Rev:0.2 5/8 IT6251 Pin No. DisplayPort Lane 3 positive output DP 51 TX3N Analog DisplayPort Lane 3 negative output DP 50 TX2P Analog DisplayPort Lane 2 positive output DP TX2N Analog DisplayPort Lane 2 negative output DP TX1P Analog DisplayPort Lane 1 positive output DP TX1N Analog DisplayPort Lane 1 negative output TX0P Analog DisplayPort Lane 0 positive output TX0N Analog DisplayPort Lane 0 negative output TXAUXP Analog DisplayPort AUX channel positive signal TXAUXN Analog DisplayPort AUX channel negative signal XTALIN Analog DisplayPort AFE crystal input (27MHz) XTALOUT Analog DisplayPort AFE crystal output (27MHz) REXT Analog External resistor for setting DisplayPort output level. Default tied to 53 57 DP 56 DP 60 DP 59 DP 48 DP 47 Analog 3 Analog 2 Analog 62 66 4 AVCC via a 820-Ohm SMD resistor. 54 19 ， Analog 71 44 TX3P QQ : Description 58 5 Direction 34 1 Pin Name 廖 R Type 51 8 DisplayPort front-end interface pins Description DBG0 NC DBG1 NC DBG2 NC NC NC Type Pin No. LVTTL 8 LVTTL 9 LVTTL 10 LVTTL 1 Description Pin No. IVDD 技 有 Type Digital logic power (1.8V) Power 6, 11, 32, 46 I/O Pin power (3.3V) Power 12 DisplayPort analog frontend power (1.8V) Power 49, 52, 55, 58, 61 DisplayPort core PLL power (1.8V) Power 64 PVCC1 DisplayPort core PLL power (1.8V) Power 63 PVCC2 Filter PLL power (1.8V) Power 4 AVCC LVDS frontend power (3.3V) Power 21, 38 ANVDD LVDS frontend analog power (1.8V) Power 16, 26, 33, 41 APVDD LVDS frontend PLL power (1.8V) Ground 31 GND Exposed GND pad Ground 65 讯 科 Pin Name 圳 Power/Ground Pins 限 公 司 ， Te l: Pin Name 18 Misc. Pins AVCC18 深 市 金 PVCC0 合 OVDD www.ite.com.tw Jul-2010 Rev:0.2 6/8 IT6251 19 ， 廖 R Functional Description PCADR 71 44 SYSRSTN 51 8 Block Diagram PCSCL Configuration PCSDA Register Block QQ : RX Decode Capture & & LINK1 DE-SSC DE/Sync & Enginer Pattern 58 5 Video Data DP TX 34 1 LVDS Link Layer DP TX TX0P/N AFE 66 4 LVDS TX1P/N TX2P/N Generator Te l: LINK2 TXAUXP/N Controller 18 RXPCLK/N RXPA1/N RXPB1/N RXPC1/N RXPD1/N RXPE1/N RXPA2/N RXPB2/N RXPC2/N RXPD2/N RXPE2/N AUX Channel Interrupt Controller HPD Figure 2. Functional block diagram of IT6251 深 圳 市 金 合 讯 科 技 有 限 公 司 ， TX3P/N www.ite.com.tw Jul-2010 Rev:0.2 7/8 IT6251 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R Package Dimensions www.ite.com.tw Figure 3. 64-pin QFN Package Dimensions Jul-2010 Rev:0.2 8/8