IT986x
Application Processor SoC
Preliminary Specification V0.1.0
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only.
For purchasing information, please contact the nearest ITE TECH sales representatives.
IT986x
This page is intentionally left blank.
www.ite.com.tw
IT986X V0.1.0
Copyright 2019 ITE Tech. Inc.
This is a Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous material issued for the products herein
referenced. Please contact ITE Tech. Inc. for the latest document(s).
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT986x, IT9862, IT9866 and IT9868 is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE Tech. Inc.
Marketing Department
9F, No. 233-2, Baoqiao Rd., Xindian Dist,
New Taipei City, 23145, Taiwan, R.O.C.
Tel:
Fax:
886-2-29126889
886-2-2910-2551, 886-2-2910-2552
If you have any marketing or sales questions, please contact:
E-mail: itesupport@ite.com.tw
You may also find the local sales representative nearest you on the ITE web site.
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
Or e-mail itesupport@ite.com.tw for more product information/services
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
www.ite.com.tw
IT986X V0.1.0
Revision History
Revision History
The contents below indicate the change between this version and the previous version only. The revision history
shown in the previous version will not remain in the following table.
Date
2020/3/24
Revise Video Input Interface Spec
Revision
2020/6/24
Modify page ii, iii
Modify 1.Features : Audio Format, SARADC
Modify 2.2.6 add MIPI I/F
Modify 3.1
Modify Table 5-1
Modify Figure 5-6, Figure 5-9
Remove 5.1.7
Modify 6. DC Characteristics : -40 degree C
Remove 5.1.1 General Description: LCD common timing generator, LVDS interface
2020/7/1
2020/7/16
2020/9/30
2020/11/30
2021/01/27
2021/06/11
2021/08/04
2021/10/20
2022/01/20
Add 5.1.7 MIPI Output Interface
Add 5.1.8 LVDS Interface
Modify Table 4-10
Modify Table 4-11
Modify 5.3.3.1
Modify 5.3.3.2
Modify Table 4-8
Modify 5.3.3.2
Modify Page12 VDD33_RTC pin number
Modify Figure 7-2
Modify Table 7-2
Modify 5.2
Modify Page3 1.Features
Modify Features Display Interface Description
Modify Features CANBUS Controller
Add IT9866-C Part Number
Modify Features ADC and SPI
Modify Chapter 6 DC Electrical Characteristics
Add IT9868-AT Part Number
Remove IT9868-AT Part Number, to be included in a separate datasheet.
Modify Features of Stacked Memory Size
Modify 3.1
Modify Ordering Information
Modify Features PWM
Modify 3. Block Diagram
Modify Table 4-10
Remove IT9866-C Part Number
CAN BUS support CAN 2.0 Only
A
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
B
www.ite.com.tw
IT986x V0.1.0
Contents
CONTENTS
1. Features ......................................................................................................................................................... 1
2. General Description........................................................................................................................................ 5
2.1 Introduction .......................................................................................................................................... 5
2.2 Multimedia Processor .......................................................................................................................... 5
2.2.1 High Performance 2D Graphics Accelerator .......................................................................... 5
2.2.2 Powerful H.264 and JPEG Engine ......................................................................................... 5
2.2.3 Powerful Audio Solution .......................................................................................................... 5
2.2.4 High performance USB2.0 I/F................................................................................................. 5
2.2.5 Flexible SPI-NAND/NOR flash controller and flash card I/Fs ................................................. 5
2.2.6 Display Interface ..................................................................................................................... 5
3. Block Diagram ................................................................................................................................................ 7
3.1 Recommended Applications Function Configuration .......................................................................... 8
4. IT986x Family IC Description ......................................................................................................................... 9
4.1 IT986x.................................................................................................................................................. 9
4.1.1 Pin Location ............................................................................................................................ 9
4.1.2 Pin Description ...................................................................................................................... 12
4.1.3 Shared GPIO Pin .................................................................................................................. 16
4.1.4 Hardware Trapping ............................................................................................................... 19
5. Function Description..................................................................................................................................... 21
5.1 Display Interface ................................................................................................................................ 21
5.1.1 General Description .............................................................................................................. 23
5.1.2 80-Type CPU Interface ......................................................................................................... 23
5.1.3 68-Type CPU Interface ......................................................................................................... 24
5.1.4 RGB with Serial Interface ..................................................................................................... 25
5.1.5 RGB with Direct Control Interface ........................................................................................ 27
5.1.6 CCIR601/656 Output Interface ............................................................................................. 28
5.1.7 MIPI Output Interface ............................................................................................................ 33
5.1.8 LVDS Interface ..................................................................................................................... 34
5.2 Host/Device USB 2.0 Interface.......................................................................................................... 37
5.3 MMC/SD Interface ............................................................................................................................. 39
5.3.1 General Description .............................................................................................................. 39
5.3.2 MMC/SD Interface Timing Diagram ...................................................................................... 40
5.3.3 Multi SD Device Connection ................................................................................................. 40
5.4 SPI Interface ...................................................................................................................................... 41
5.5 Digital Audio Interface ....................................................................................................................... 43
5.5.1 General Description .............................................................................................................. 43
5.5.2 Digital Audio Interface Implementation ................................................................................. 44
5.5.3 Audio Interface Data Formats ............................................................................................... 44
5.6 UART and IrDA Interface .................................................................................................................. 45
5.7 DMA Controller .................................................................................................................................. 45
5.8 Ethernet MAC Interface ..................................................................................................................... 45
5.9 PLL Interface ..................................................................................................................................... 46
5.10 2D Graphice Engine .......................................................................................................................... 46
5.11 JPEG ................................................................................................................................................. 46
5.12 Video ................................................................................................................................................. 46
5.13 SAR ADC ........................................................................................................................................... 47
5.14 General-Purpose I/O ......................................................................................................................... 47
6. DC Characteristics ....................................................................................................................................... 49
7. AC Characteristics........................................................................................................................................ 51
7.1 Reset Timing ..................................................................................................................................... 51
7.2 Power Sequence ............................................................................................................................... 51
8. Package Information .................................................................................................................................... 53
8.1 IT986x Family Package Information .................................................................................................. 53
9. Ordering Information .................................................................................................................................... 55
i
www.ite.com.tw
IT986x V0.1.0
IT986x
FIGURES
Figure 5-1. Connection of IT986x Family to 80-Type CPU Interface LCM ........................................................ 23
Figure 5-2. 80-Type CPU Interface Timing........................................................................................................ 24
Figure 5-3. Connection of IT986x Family to 68-Type CPU Interface LCM ........................................................ 24
Figure 5-4. 68-Type CPU Interface Timing........................................................................................................ 25
Figure 5-5. Connection of IT986x Family to RGB with Serial Interface LCM .................................................... 25
Figure 5-6. RGB Timing (for data) ..................................................................................................................... 26
Figure 5-7. RGB Timing (for command) ............................................................................................................ 27
Figure 5-8. Connection of IT986x Family to RGB with Direct Control Interface LCM ....................................... 27
Figure 5-9. RGB with Direct Control Interface Timing (for data) ....................................................................... 28
Figure 5-10. Connection of IT986x Family to Host Processor with CCIR601 Interface .................................... 29
Figure 5-11. Connection of IT986x Family to Host Processor with CCIR656 Interface .................................... 29
Figure 5-12. CCIR601 Output Interface Timing ................................................................................................. 29
Figure 5-13. CCIR656 Output Interface Timing ................................................................................................. 31
Figure 5-14. Connection of IT986x Family to MIPI Panel .................................................................................. 33
Figure 5-15. Line Levels in HS and LP Modes .................................................................................................. 34
Figure 5-16. High-Speed Data Transmission in Bursts ..................................................................................... 34
Figure 5-17. Connection of IT986x Family to JEIDA 24-bits LVDS panel ......................................................... 34
Figure 5-18. JEIDA 24-bits Interface Timing ..................................................................................................... 35
Figure 5-19. Connection of IT986x Family to VESA 18-bits LVDS panel ......................................................... 35
Figure 5-20. VESA 18-bits Interface Timing ...................................................................................................... 36
Figure 5-21. Connection of IT986x Family to VESA 24-bits LVDS panel ......................................................... 36
Figure 5-22. VESA 24-bits Interface Timing ...................................................................................................... 37
Figure 5-23. MMC/SD Interface Timing Diagram .............................................................................................. 40
Figure 5-24. Serial Input Timing ........................................................................................................................ 41
Figure 5-25. Serial Output Timing ..................................................................................................................... 42
Figure 5-26. Block Diagram of NOR Interface ................................................................................................... 42
Figure 5-27. IIS Audio Interface ......................................................................................................................... 44
Figure 5-28. MSB Left Justified Interface .......................................................................................................... 45
Figure 7-1. Reset Timing ................................................................................................................................... 51
Figure 7-2. Power Sequence Timing ................................................................................................................. 51
TABLES
Table 4-1. IT986x Pins Listed in Numeric Order ............................................................................................... 10
Table 4-2. IT986x Pins Listed in Alphabetical Order ......................................................................................... 11
Table 4-3. Pin Description of Supplies Signals ................................................................................................. 12
Table 4-4. Pin Description of USB Signals ........................................................................................................ 12
Table 4-5. Pin Description of MIPI/LVDS Signals ............................................................................................. 12
Table 4-6. Pin Description of ADDA Signals ..................................................................................................... 12
Table 4-7. Pin Description of SARADC Signals ................................................................................................ 13
Table 4-8. Pin Description of GPIO Signals ...................................................................................................... 13
Table 4-9. Pin Description of Misc Signals ........................................................................................................ 14
Table 4-10. Shared GPIO Pin Table .................................................................................................................. 16
Table 4-11. GPIO Pin Description ..................................................................................................................... 17
Table 4-12. SPI Host Interface when HOST_CFG == 01.................................................................................. 18
Table 4-13. IIC Host Interface when HOST_CFG == 10 ................................................................................... 18
Table 4-14. IT986x Hardware Trapping ............................................................................................................. 19
Table 5-1. LCD Interface General Pin Mapping ................................................................................................ 21
ii
www.ite.com.tw
IT986x V0.1.0
Contents
Table 5-2. LCD with RGB Interface Pin Mapping for RGB565 and RGB666 .................................................... 21
Table 5-3. LCD with RGB Interface Pin Mapping for RGB888 .......................................................................... 22
Table 5-4. LCD Pin Share with GPIO Table (TBD) ........................................................................................... 23
Table 5-5. CCIR601 Output Interface Timing Table .......................................................................................... 29
Table 5-6. SAV Code and EAV Code ................................................................................................................ 31
Table 5-7. CCIR656 Output Interface Timing Table .......................................................................................... 32
Table 5-8. Dynamic Characteristics of DP/DM .................................................................................................. 37
Table 5-9. Static Characteristics of DP/DM ....................................................................................................... 38
Table 5-10. MMC/SD Interface Timing Table .................................................................................................... 40
Table 5-11. NOR Interface AC Timing............................................................................................................... 41
Table 5-12. Pin Share for AXISPI Interface ....................................................................................................... 42
Table 7-1. Reset Timing Table .......................................................................................................................... 51
Table 7-2. Power Sequence Table .................................................................................................................... 51
iii
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
iv
www.ite.com.tw
IT986x V0.1.0
Features
-
1. Features
Host Processor
- 800MHz 32-bit ARM9 CPU1
- 32KB instruction cache
- 32KB data cache
- 400MHz 32-bit ARM9 CPU2
- 16KB instruction cache
- 16KB data cache
8 bits data of MMCA v4.3
Compliant with SD/SDHC/SDXC
FAT16/FAT32 boot loader
NOR Flash Controller
- Dedicated high speed SPI NAND/NOR
controller.
- Supports SPI NAND/NOR flash
- Supports SPI serial mode, dual mode and
quad mode
- Support maximum operating frequency at
80Mhz without pin share
Audio Format
- Supports audio CODEC
- MP3
Ethernet MAC
- Compliant with full IEEE 802.3-2002
specifications
- Supports IEEE 802.1Q VLAN tag detection
for reception frames
- Supports CSMA/CD Protocol for HalfDuplex operation
- Supports IEEE 802.3x flow-control for FullDuplex operation
- Supports IEEE 1588-2002 Time stamping
on the transmit and received frames
- IEEE 802.3 compliant RMII PHY interface
Micro Controller
- 324MHz 32-bit RISC CPU
- 16KB SRAM for instruction/data access
Display Interface
- 2160x1080 16/18/24 bpp
(RGB565/RGB666/RGB888)
- Supports 16/18/24 bits RGB I/F and
8/9/16/18 bits CPU I/F
- Hardware 180°, mirror and flip rotate
- Supports CCIR601/CCIR656 interface
- Support LVDS interface (Maximum
resolution: 1920X1080 pixel)
- Maximum CLK rate of 140MHz
- Support MIPI interface (Maximum
resolution:2160X1080 pixel)
- D-PHY specification, Version 1.0,
1Gbps/lane
Audio Input/Output Interface
- Record Five I2S interface
- Playback One I2S interface
- One embedded ADDA device:
sample rates: 8~96KHz
sample sizes: 16~24 bits
2D Graphics Acceleration
- Bit Block Transfer (BitBlt) with ROP3
operation
- Supports mask plan with 1bpp, 2bpp, 4bpp
and 8bpp format.
- Supports color expansion with 1bpp, 2bpp,
4bpp and 8bpp format
- Coordinates transform
- Line draw with dash style
- One clipping window
Video Input Interface
- Supports BT601:16/20-bit YCbCr 4:2:2
- Supports BT656:8/10/12-bit YCbCr 4:2:2
- Supports HD BT1120 interface
- Resolution: 1080p@ 60 fps(1920X1080)
USB Host/Device
- Provides one host/device controller
- Compliant with USB specification version
2.0
- Compatible with EHCI 1.0
- Supports point-to-point communications
with one HS/FS/LS device
- Both host and device support
isochronous/interrupt/control/bulk transfers
- Compatible with EHCI data structures
SD/SDIO 3.0 Controller
- Two MMC/SD/SDIO controller
- Fully compliant with MMCA v4.3
1
www.ite.com.tw
IT986x V0.1.0
IT986x
Video Signal Processor
- Image and video scaling engine
- 4-Tap scaling filter
- Configurable filter coefficients
- 2D deinterlace filter
- 3D deinterlace filter
- Support 2 layer High color OSD
-
-
JPEG Encoder/Decoder
- Fully compliant with Baseline JPEG
standard ISO/IEC 10918
- Supports up to 256 million pixel (16376 *
16376)
- Supports 422, 420, 444 decode
- Supports 422, 420 encode
- Supports downloadable Quantization and
Huffman table
- Supports motion JPEG for 720p@30fps
(1280x720)
Each port can separately trigger the GPIO
interrupt when it is programmed as input
pin.
Each port interrupt generation can be
triggered by rising edge, falling edge, both
edges, or high/low level when the interrupt
option is set.
IIC
- Provides Four IIC interfaces
- All with fully mux GPIO output
- Supports standard (100kHz), and fast mode
(400kHz) through programming the clock
division register
- Supports 7-bit, 10-bit and general call
addressing mode
- Glitch suppression throughout the debounce circuit
- Programmable slave address
- Master-transmit, Master-receive, Slavetransmit and Slave-receive modes provided
- Configurable multi-master mode supported
- Slave mode general call address detection
Video Decoder
- Support H.264/AVC decoding
1080p30@40Mbps
- Support error detection and concealment
UART/IrDA
- Six UART interfaces
- All with fully MUX GPIO output
- Baud rate up to 6.25M bps
- Firmware compatible with high-speed NS
16C550A UART
- IrDA 1.3 SIR with up to 115.2kbps data rate
- SIR pulse width programmable as 1.6us or
3/16 of the baud-rate pulse width
- Supports IrDA 1.3 FIR
- Multi-frame transmission and reception in
FIR mode
Cypher Engine
- Compliant with the Publication 197 from
NIST (AES) encryption/decryption with 128bit key size
- Supports ECB, CBC, CFB, CTR and OFB
operation mode
Compress Engine
- BriefLZ encode/decode
- UCL decode
DMA
- Provides 8 configurable DMA channels
- Supports chain transfer
- Memory-to-memory, memory-to-peripheral,
and peripheral-to-peripheral transfer
- Group round-robin arbitration scheme with 4
priority levels
- Supports 8-, 16-, 32 and 64-bit wide data
transaction
- Supports big-endian and little-endian
Interrupt Controller
- Provides both edge and level-triggered
interrupt sources with positive and negative
directions
- Provides de-bounce circuit for interrupt
source
PWM
- Provides 8 independent 32-bit timers with
PWM
- All with fully MUX GPIO output
- Programmable duty cycle and frequency
- Supports external clock source
- It can merge two timers into a 64-bit timer.
- Supports incrementing and decrementing
mode
Power Management
- Flexible clock divider to slow down clock
- Dynamic gating clock
- Separate clock source to disable unused
peripherals
- Wakeup from external event
GPIO
- Independent input, output and output enable
buses for bi-directional I/O pins
2
www.ite.com.tw
IT986x V0.1.0
Features
SPI
- Supports TI SSP, Motorola SPI, National
Semiconductor Microwire, and SPIDIF
interface
- Supports master and slave modes
- Internally or externally controlled serial bit
clock
- Internally or externally controlled frame/sync
- Programmable frame/sync polarity
- Programmable serial bit clock polarity,
phase, and frequency
- Programmable serial bit data sequence
(MSB or LSB first)
- Programmable threshold interrupt of
transmit/receive FIFO
- Supports 2 independent SPI interface
Watch Dog
- During timeout, outputs are system reset or
interrupt.
- 32-bit down counter
- A variable time-out period of reset
CANBUS Controller
- Provides 2 independent CANBUS controller
- All with fully MUX GPIO output
- Supports CAN 2.0B
- Defines Data rates up to 1Mbit/s
- Single Shot Transmission Mode and
Transceiver Standby Mode
- Time-stamping : ISO 11898-4 TimeTriggered CAN and CiA 603 time-stamping
RTC
- Separated second, minute, hour, and day
counter
- Programmable auto second, minute, hour or
day alarm
- Generates power on signal when alarm
occurs
Booting
- Configurable booting media select
- SD/MMC/eMMC(4-bit) booting
- SPI-NAND booting
- NOR booting
Remote in/out Controller
- Hardware programmable to receive remote
controller signal.
- Transfer data to remote signal
- Remote in signal with fully mux gpio input
SARADC
- Configurable 8 channels input share the
ADC
- 12-bits raw data per sample
- 1 MHz sample rate shared by 8 channels
- Single / Continuous / Group scan mode
- Software timer trigger start
Wiegand in/out Controller
- Provides two Wiegand in/out interface
- Support Wiegand 26/34/37 mode
- Supports up to maximum 128-bit code
length
- Auto detects wiegand in code length
Stacked Memory Size
- IT9862 Stacked 128Mb DDR2 Memory
- IT9866 Stacked 512Mb DDR2 Memory
- IT9868 Stacked 1Gb DDR3 Memory
3
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
4
www.ite.com.tw
IT986x V0.1.0
General Description
2. General Description
2.1
Introduction
The IT986x family is high performance HD display and high integrated SoC. (The IT986x family includes IT9862,
IT9866 and IT9868 package.) It equips 2D Graphics Accelerator allowing for some special user interface
designing, JPEG/H.264 HD decoding engine allowing users to have smooth experience while they are watching
images and clips, audio engines allowing users to have joyful feeling while they are watching images and surely
some other useful interfaces for users to have more flexible usage with their platform.
2.2
2.2.1
Multimedia Processor
High Performance 2D Graphics Accelerator
This engine supports bitblt, blending, rotation, scale and perspective transform function.
2.2.2
Powerful H.264 and JPEG Engine
The engines in the IT986x family offer users the ability to play those clips by video stream. The H.264 decode
engine can perform up to 1920x1080p@30fps size clip decoding. Except for H.264 decode, IT986x family have
JPEG engine inside. The JPEG engine can perform up to 256M-pixel still JPEG decoding and perform up to
1280x720p@30fps motion JPEG clip decoding. There is a video scaling engine for scaling up or down to the
target display size.
2.2.3
Powerful Audio Solution
IT986x family embeds a 32-bit CPU and audio AD/DA. It can support MPEG-1 and MPEG-2 layer 2 audio decoder,
MP3 decoder. Besides, it provides IIS as well and users can freely choose to whether to adopt another high
performance IIS interface DAC or not when the performance and cost factors are taken into consideration.
2.2.4
High performance USB2.0 I/F
IT986x family supports a USB2.0 host or a USB2.0 device I/F, through which users can experience a high-speed
data transfer.
2.2.5
Flexible SPI-NAND/NOR flash controller and flash card I/Fs
IT986x family have various external cards, I/F, SPI-NAND flash I/F and NOR flash I/F. About external cards I/F,
IT986x family build in SD3.0/MMC card controllers. If users want some other external cards I/F, IT986x family
provide a USB host I/F allowing for an external card bus chip.IT986x family provide SPI-NAND and NOR flash
I/F. Besides SPI-NAND, NOR and SD are the other solutions for users to choose as a booting code storage
space.
2.2.6
Display Interface
IT986x family supports various LCD I/Fs, such as RGB I/F, LVDS I/F, MIPI I/F and can support resolution up to
1920x1080 in the true color mode based on all of them. With the flexible display I/F, it will be easier to select the
appreciate LCM required for users’ platforms.
5
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
6
www.ite.com.tw
IT986x V0.1.0
Block Diagram
3. Block Diagram
7
www.ite.com.tw
IT986x V0.1.0
IT986x
3.1
Recommended Applications Function Configuration
Memory
CPU
IT9862
IT9866
IT9868
128Mb
DDR2
512Mb
DDR2
1Gb
DDR3
Dual ARM9 800M + Dual ARM9 800M + Dual ARM9 800M +
400MHz
400MHz
400MHz
Video Function
-
720p H.264
DECODER
1080p H.264
DECODER
Panel Interface
RGB, MIPI, LVDS
RGB, MIPI, LVDS
RGB, MIPI, LVDS
Panel Resolution
800*480
1280*800
2160*1080
Application
Package
Home Appliances,
Home Appliances,
Home Appliances,
Automotive Smart
Automotive Smart
Automotive Smart
Display
Display, Smart Home Display, Smart Home
LQFP 128 pins (pin to pin)
8
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
4. IT986x Family IC Description
4.1
4.1.1
IT986x
Pin Location
IT986x
9
www.ite.com.tw
IT986x V0.1.0
IT986x
Table 4-1. IT986x Pins Listed in Numeric Order
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Signal
EXTPWRUP
PWREN
OSCIO
OSCI
VDD33_RTC
VDD33A_XTL
XIN
XOUT
VDD11A_PLL
VDD11_CORE
RSTN
ENTEST
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
VDD33_IO
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
VDD33_IO
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Signal
GPIO19/XAIN0
GPIO20/XAIN1
GPIO21/XAIN2
GPIO22/XAIN3
GPIO23/XAIN4
GPIO24/XAIN5
GPIO25/XAIN6
GPIO26/XAIN7
VDD33A_SAR
R240GND
R240V18
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEMCK
VDD11A_MEMPLL
VDD11_CORE
VDD11_CORE
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
VDD33_IO
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
Pin
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Signal
USBRREF
GNDA_USB
USBDM
USBDP
VDD33_IO
GPIO38
GPIO40
GPIO41
VDD11_CORE
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
VDD33_IO
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
Pin
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Signal
VDD11_CORE
GPIO64
GPIO65
GPIO66
GPIO67
VDD11_CORE
VDD33_IO
CAP12A_MIPI
MIPIDP3/LVDSP4
MIPIDN3/LVDSN4
MIPIDP2/LVDSP3
MIPIDN2/LVDSN3
MIPICKP/LVDSP2
MIPICKN/LVDSN2
MIPIDP1/LVDSP1
MIPIDN1/LVDSN1
MIPIDP0/LVDSP0
MIPIDN0/LVDSN0
VDD11_CORE
VDD11_CORE
VDD11_CORE
RMICIP
RMICIN
LMICIP
LMICIN
MICBIAS
VDD33A_ADDA
VCM
GND_ADDA
RHPOUT
LHPOUT
VDD33A_ADDA
10
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
Table 4-2. IT986x Pins Listed in Alphabetical Order
Signal
CAP12A_MIPI
ENTEST
EXTPWRUP
GND_ADDA
GNDA_USB
GPIO0
GPIO1
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19/XAIN0
GPIO2
GPIO20/XAIN1
GPIO21/XAIN2
GPIO22/XAIN3
GPIO23/XAIN4
GPIO24/XAIN5
GPIO25/XAIN6
GPIO26/XAIN7
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
Pin
104
12
1
125
66
13
14
24
25
26
27
28
29
30
31
33
15
34
35
36
37
38
39
40
53
54
55
16
56
57
59
60
Signal
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
Pin
61
62
63
64
70
17
71
72
74
75
76
77
78
79
80
81
18
82
83
84
85
86
88
89
90
91
92
19
93
94
95
96
Signal
GPIO64
GPIO65
GPIO66
GPIO67
GPIO7
GPIO8
GPIO9
LHPOUT
LMICIN
LMICIP
MICBIAS
MIPICKN/LVDSN2
MIPICKP/LVDSP2
MIPIDN0/LVDSN0
MIPIDP0/LVDSP0
MIPIDN1/LVDSN1
MIPIDP1/LVDSP1
MIPIDN2/LVDSN3
MIPIDP2/LVDSP3
MIPIDN3/LVDSN4
MIPIDP3/LVDSP4
OSCI
OSCIO
PWREN
R240GND
R240V18
RHPOUT
RMICIN
RMICIP
RSTN
USBDM
USBDP
Pin
98
99
100
101
20
21
22
127
121
120
122
110
109
114
113
112
111
108
107
106
105
4
3
2
42
43
126
119
118
11
67
68
Signal
USBRREF
VCM
VDD11_CORE
VDD11_CORE
VDD11_CORE
VDD11_CORE
VDD11_CORE
VDD11_CORE
VDD11_CORE
VDD11A_MEMPLL
VDD11_CORE
VDD11_CORE
VDD11A_PLL
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEM
VDD18_MEMCK
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_RTC
VDD33A_ADDA
VDD33A_ADDA
VDD33A_SAR
VDD33A_XTL
XIN
XOUT
Pin
65
124
10
51
52
73
97
102
117
50
116
115
9
44
45
46
47
48
49
23
32
58
69
87
103
3
123
128
41
6
7
8
11
www.ite.com.tw
IT986x V0.1.0
IT986x
4.1.2
Pin Description
Table 4-3. Pin Description of Supplies Signals
Pin(s) No.
104
10, 51, 52,
73, 97, 102,
115,116,117
50
9
44, 45, 46,
47, 48
49
23,32,58,69,
87,103
5
123, 128
41
6
125
66
Symbol
CAP12A_MIPI
VDD11_CORE
Attribute
Power
Power
Power
-
Description
MIPI Supply 1.2V
Digital Core Supply 1.1V
VDD11A_MEMP
LL
VDD11A_PLL
VDD18_MEM
Power
-
Memory phy PLL Supply 1.1V
Power
Power
-
System PLL Supply 1.1V
Memory Chip Supply 1.8V
VDD18_MEMCK
VDD33_IO
Power
Power
-
Memory Phy clock tree Supply 1.8V power
Chip IO Supply 3.3V
VDD33_RTC
VDD33A_ADDA
VDD33A_SAR
VDD33A_XTL
GND_ADDA
GNDA_USB
Power
Power
Power
Power
Ground
Ground
-
RTC Supply 3.3V
ADDA Supply 3.3V
SAR_ADC Supply 3.3V
RTC crystal Supply 3.3V
Audio ADDA ground pin
USB ground pin
Table 4-4. Pin Description of USB Signals
Pin(s) No.
67
68
65
Symbol
USBDM
USBDP
USBRREF
Attribute
I/O
I/O
I/O
Power
VDD33_IO
VDD33_IO
VDD33_IO
Description
USB data in data negative pin terminal
USB data in data positive pin terminal
USB RREF current source, It needs to connect the
12-kΩ resistor
Table 4-5. Pin Description of MIPI/LVDS Signals
MIPIDN0/LVDSN0
MIPIDP0/LVDSP0
MIPIDN1/LVDSN1
MIPIDP1/LVDSP1
MIPIDN2/LVDSN3
Attr
ibut
e
O
O
O
O
O
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
107
MIPIDP2/LVDSP3
O
VDD33_IO
106
MIPIDN3/LVDSN4
O
VDD33_IO
105
MIPIDP3/LVDSP4
O
VDD33_IO
110
MIPICKN/LVDSN2
O
VDD33_IO
109
MIPICKP/LVDSP2
O
VDD33_IO
Pin(s) No.
Symbol
114
113
112
111
108
Power
Description
MIPI/ LVDS differential signal pair 0
MIPI/ LVDS differential signal pair 0
MIPI/ LVDS differential signal pair 1
MIPI/ LVDS differential signal pair 1
MIPI differential signal pair 2/ LVDS
differential signal pair 3
MIPI differential signal pair 2/ LVDS
differential signal pair 3
MIPI differential signal pair 3/ LVDS
differential signal pair 4
MIPI differential signal pair 3/ LVDS
differential signal pair 4
MIPI differential signal pair CK/ LVDS
differential signal pair 2
MIPI differential signal pair CK/ LVDS
differential signal pair 2
Table 4-6. Pin Description of ADDA Signals
Pin(s) No.
127
126
Symbol
LHPOUT
RHPOUT
Attribute
O
O
Power
VDD33A_ADDA
VDD33A_ADDA
Description
Analog headphone output of the left channel
Analog headphone output of the right channel
12
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
Pin(s) No.
124
122
121
Symbol
VCM
MICBIAS
LMICIN
Attribute
I
O
I
Power
VDD33A_ADDA
VDD33A_ADDA
VDD33A_ADDA
120
LMICIP
I
VDD33A_ADDA
119
RMICIN
I
VDD33A_ADDA
118
RMICIP
I
VDD33A_ADDA
Description
Analog common-mode voltage
Analog microphone bias output
Analog microphone input of the left channel
Negative channel
Analog microphone input of the left channel
Positive channel
Analog microphone input of the right channel
Negative channel
Analog microphone input of the right channel
Positive channel
Table 4-7. Pin Description of SARADC Signals
Pin(s) No.
33
Symbol
XAIN0
Attribute
I
Power
VDD33A_SAR
34
XAIN1
I
VDD33A_SAR
35
XAIN2
I
VDD33A_SAR
36
XAIN3
I
VDD33A_SAR
37
XAIN4
I
VDD33A_SAR
38
XAIN5
I
VDD33A_SAR
39
XAIN6
I
VDD33A_SAR
40
XAIN7
I
VDD33A_SAR
Description
Analog voltage signal input for SARADC
channel0
Analog voltage signal input for SARADC
channel1
Analog voltage signal input for SARADC
channel2
Analog voltage signal input for SARADC
channel3
Analog voltage signal input for SARADC
channel4
Analog voltage signal input for SARADC
channel5
Analog voltage signal input for SARADC
channel6
Analog voltage signal input for SARADC
channel7
Table 4-8. Pin Description of GPIO Signals
Pin(s) No.
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
33
34
35
36
37
38
Symbol
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
Attribute
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
Description
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19 or XAIN0(SAR ADC channel0)
GPIO20 or XAIN1(SAR ADC channel1)
GPIO21 or XAIN2(SAR ADC channel2)
GPIO22 or XAIN3(SAR ADC channel3)
GPIO23 or XAIN4(SAR ADC channel4)
GPIO24 or XAIN5(SAR ADC channel5)
13
www.ite.com.tw
IT986x V0.1.0
IT986x
Pin(s) No.
39
40
53
54
55
56
57
59
60
61
62
63
64
70
71
72
74
75
76
77
78
79
80
81
82
83
84
85
86
88
89
90
91
92
93
94
95
96
98
99
100
101
105
106
107
108
109
110
111
112
113
114
Symbol
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
Attribute
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
VDD33_IO
Description
GPIO25 or XAIN6(SAR ADC channel6)
GPIO26 or XAIN7(SAR ADC channel7)
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
Table 4-9. Pin Description of Misc Signals
Pin(s) No.
3
4
7
8
Symbol
OSCIO
OSCI
XIN
XOUT
Attribute
O
I
I
I
Power
VDD11A_PLL
VDD11A_PLL
VDD33A_XTL
VDD33A_XTL
Description
RTC Crystal 32.768KHz Output
RTC Crystal 32.768KHz Input
System Crystal 12MHz Input
System Crystal 12MHz output
14
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
Pin(s) No.
11
12
42
Symbol
RSTN
ENTEST
R240GND
Attribute
I
I
I
Power
VDD33_IO
VDD33_IO
VDD18_MEM
43
R240V18
I
VDD18_MEM
Description
Reset
Test Enable
Pad to the precise internal resistor for compensation the
pull-up driver. Tied to Ground through a 240 ohm resistor
with 1% tolerance.
Pad to the precise internal resistor for compensation the
pull-down driver. Tied to 1.8V through a 240 ohm resistor
with 1% tolerance.
15
www.ite.com.tw
IT986x V0.1.0
IT986x
4.1.3
Shared GPIO Pin
Table 4-10. Shared GPIO Pin Table
Pin Name
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19/XAIN0
GPIO20/XAIN1
GPIO21/XAIN2
GPIO22/XAIN3
GPIO23/XAIN4
GPIO24/XAIN5
GPIO25/XAIN6
GPIO26/XAIN7
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
Mode 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
Mode 1
Mode 2
AXISPI_CS0
AXISPI_D0
AXISPI_D1
AXISPI_D2
AXISPI_D3
AXISPI_CLK
AXISPI_CS1
Mode 3
Mode 4
SPI1_CLK
SPI1_CS0
SPI1_DO
SPI1_DI
SPI0_CLK
SPI0_CS0
SPI0_DO
SPI0_DI
SPI0_CS1
SPI0_CLK
SPI0_CS0
RX_ZD1
RX_ZD2
RX_ZD3
SD0_D0
SD0_D1
SD0_D2
SD0_D3
SD1_CLK
SD0_CMD
SD0_CLK
SD0_D0
SD0_D1
SD0_D2
SD0_D3
WO1_D0
WO1_D1
IrDA_RXL
IrDA_TX
WO0_D0
WO0_D1
WO1_D0
WO1_D1
MDIO
MDC
TXD1
TXD0
TXEN
TXC
RX_CRS_DV
RXD0
RXD1
RXER
INTB
LDCLK
LD1*1
LD2*1
LD3*1
LD4*1
LD5*1
LD6*1
LD7*1
LD8*1
LD9*1
LD10*1
LD11*1
LD12*1
LD13*1
LD14*1
LD15*1
LD16*1
LD17*1
LD18*1
SPI0_CLK
SPI0_CS0
SPI0_DO
SD1_CLK
SD1_CMD
SD1_D0
SD1_D1
SD1_D2
SD1_D3
VD0*2
VD2*2
VD3*2
VD4*2
VD5*2
VD6*2
VD7*2
VD8*2
VD9*2
VD10*2
VD11*2
VD12*2
VD13*2
VD14*2
VD15*2
VD16*2
VD17*2
VD18*2
VD19*2
SPI0_DI
SPI1_CLK
SPI1_CS0
SPI1_DO
SPI1_DI
SPI1_CLK
SPI1_DO
SPI1_DI
SPI1_CS1
WO0_D0
WO0_D1
WO1_D0
WO1_D1
SD0_CLK
SD0_CMD
SD0_D0
SD0_D1
SD0_D2
SD0_D3
SD0_D4
WO0_D0
WO0_D1
WO1_D0
WO1_D1
SD1_CLK
SD1_CMD
SD1_D0
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD1_D5
LDCLK
SD1_D6
SD1_D7
RX_ZCLK
RX_ZWS
RX_ZD0
16
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
Pin Name
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
MIPIDP3/LVDSP4
MIPIDN3/LVDSN4
MIPIDP2/LVDSP3
MIPIDN2/LVDSN3
MIPICKP/LVDSP2
MIPICKN/LVDSN2
MIPIDP1/LVDSP1
MIPIDN1/LVDSN1
MIPIDP0/LVDSP0
MIPIDN0/LVDSN0
Mode 0
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
Mode 1
LD19*1
LD20*1
LD21*1
LD22*1
LD23*1
LD24*1
LD25*1
LD26*1
LD27*1
LD28*1
LD29*1
LD30*1
LD31*1
LD32*1
LD33*1
LD34*1
LD35*1
LD36*1
LD37*1
LD38*1
Mode 2
VD20*2
VD21*2
VD22*2
VD23*2
VD24*2
VD25*2
Mode 3
SD0_D5
SD0_D6
SD0_D7
SD1_D1
SD1_CMD
SD1_CLK
Mode 4
RX_AMCLK
LDCLK
RX_ZCLK
RX_ZWS
RX_ZD0
RX_AMCLK
LDCLK
Note *1: Those pins can be assigned from any LD1 to LD38.
Note *2: Those pins can be assigned from any VD0 to VD25.
Table 4-11. GPIO Pin Description
Pin Name
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default reset)
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
Power
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOA
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOB
Description
-
17
www.ite.com.tw
IT986x V0.1.0
IT986x
Pin Name
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default reset)
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
Power
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOB
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
VDD_IOC
Description
HOST_CFG0
HOST_CFG1
BOOT_CFG0
BOOT_CFG1
Notes: GPIO64~GPIP67 are for the hardware trap. There is pull-high/low resistance on I/O. It cannot drive the
value on the external device when the system is resetting.
Table 4-12. SPI Host Interface when HOST_CFG == 01
Pin Name
GPIO0
GPIO1
GPIO2
GPIO3
Type
Input
Input
Input
Output
Default
HighZ
HighZ
HighZ
0
Description
SPI Slave CLK
SPI Slave CS#
SPI Slave DIN
SPI Slave DOUT
Table 4-13. IIC Host Interface when HOST_CFG == 10
Pin Name
GPIO0
GPIO1
Type
I/O
I/O
Default
HighZ
HighZ
Description
IIC SCL
IIC SDA
18
www.ite.com.tw
IT986x V0.1.0
IT986x IC Description
4.1.4
Hardware Trapping
Table 4-14. IT986x Hardware Trapping
Pin Name
GPIO66
GPIO67
Symbol
BOOT_CFG0
BOOT_CFG1
GPIO63
ARM_CFG
GPIO64
GPIO65
HOST_CFG0
HOST_CFG1
Description
Boot Configuration
00: booting from SD/MMC/EMMC
01: booting from NOR
10: booting from SPI NAND
11: co-operative mode
ARM Configuration
0: Normal(Default)
Host Configuration
00: select JTAG interface
01: select SPI interface
10: select IIC interface
11: uses as DGPIO[0-3]
19
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
20
www.ite.com.tw
IT986x V0.1.0
Function Description
5. Function Description
5.1
Display Interface
The IT986x family supports 8/9/16/18 bits of CPU interface, 16/18/24 bits of RGB interface, and CCIR601
interface. The IT986x family supports both of LCD modules (LCM) with and without memory. The programmable
interface timing is designed to fit most LCMs. Hereunder is the pin share mapping on each different mode.
Table 5-1. LCD Interface General Pin Mapping
Pin Name
RGB I/F
CPU I/F
LVSYNC
LHSYNC
LDCLK
LDEN
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
LD18
LD19
LD20
LD21
LD22
LD23
LCSN
LSA0
LSDA
LSCK
VSYNC
HSYNC
DCLK
DEN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22 / CTG4
D23 / CTG5
CS0 / CTG7
A0 / CTG6
SDA
SCK / CTG3
XWR
XRS
CCIR
601/656
VSYNC
HSYNC
DCLK
DEN
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
CS0
CTG4
CTG5
CS0 / CTG7
A0 / CTG6
SDA
SCK / CTG3
Table 5-2. LCD with RGB Interface Pin Mapping for RGB565 and RGB666
Color
Mode
Panel
Interface
Timing
Sequence
LD0
LD1
RGB565
RGB666
16-bit
6-bit
9-bit
18-bit
t/pixel
t1/pixel
t2/pixel
t3/pixel
t1/pixel
t2/pixel
t/pixel
B0
B1
R0
R1
G0
G1
B0
B1
G3
G4
B0
B1
B0
B1
21
www.ite.com.tw
IT986x V0.1.0
IT986x
Color
Mode
Panel
Interface
Timing
Sequence
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
RGB565
RGB666
16-bit
6-bit
9-bit
18-bit
t/pixel
t1/pixel
t2/pixel
t3/pixel
t1/pixel
t2/pixel
t/pixel
B2
B3
B4
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R2
R3
R4
R5
G2
G3
G4
G5
B2
B3
B4
B5
G5
R0
R1
R2
R3
R4
R5
B2
B3
B4
B5
G0
G1
G2
B2
B3
B4
B5
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
Table 5-3. LCD with RGB Interface Pin Mapping for RGB888
Color
Mode
Panel
Interface
Timing
Sequence
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
LD18
LD19
LD20
LD21
LD22
LD23
RGB888
9-bit/mode 1
9-bit/mode 2
18-bit
24-bit
t1/pixel
t2/pixel
t3/pixel
t1/pixel
t2/pixel
t3/pixel
t1/pixel
t2/pixel
t/pixel
R0
R1
R2
R3
R4
R5
R6
R7
GND
G0
G1
G2
G3
G4
G5
G6
G7
GND
B0
B1
B2
B3
B4
B5
B6
B7
GND
GND
R0
R1
R2
R3
R4
R5
R6
R7
GND
G0
G1
G2
G3
G4
G5
G6
G7
GND
B0
B1
B2
B3
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
R6
R7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
22
www.ite.com.tw
IT986x V0.1.0
Function Description
Table 5-4. LCD Pin Share with GPIO Table (TBD)
5.1.1
General Description
80-type CPU interface
68-type CPU interface
RGB with serial interface
RGB with direct control interface
CCIR601/CCIR656 output interface
5.1.2
80-Type CPU Interface
The figure below illustrates the implementation for interfacing the IT986x family to an 80-type CPU interface
LCM. IT986x family can support dual display for this interface.
IT986x family
IT970 family
LCD panel
LVSYNC
LHSYNC
LDCLK
LDEN
LD[17:0]
LCSN
LSA0
LSDA
LSCK
WR
RS
RD
LD[17:0]
LCS#
Figure 5-1. Connection of IT986x Family to 80-Type CPU Interface LCM
The timing for 80-type CPU interface is shown in the following figure. There is an internal clock DHCLK. By
adjusting the timing parameters T 1 ~ T8, which are relative to DHCLK, it can satisfy the timing requirement of
LCD panels.
23
www.ite.com.tw
IT986x V0.1.0
IT986x
0
1
2
3
4
5
6
0
1
2
3
4
5
6
DHCLK
(internal clock)
T1
T2
LCSN
T6
T3
LVSYNC
T5
T7
T4
LDEN
T8
LHSYNC,
LD[17:0]
Figure 5-2. 80-Type CPU Interface Timing
5.1.3
68-Type CPU Interface
The figure below illustrates the implementation for interfacing the IT986x family to the LCM with a 68-type CPU
interface. IT986x family can support dual displays for this interface.
IT986x
family
IT970 family
LCD panel
LVSYNC
LHSYNC
LDCLK
LDEN
LD[17:0]
LCSN
LSA0
LSDA
LSCK
E
RS
R/W
LD[17:0]
LCS#
Figure 5-3. Connection of IT986x Family to 68-Type CPU Interface LCM
The timing for 68-type CPU interface is shown in the following figure. There is an internal clock DHCLK. By
adjusting the timing parameters T 1 ~ T8, which are relative to DHCLK, it can satisfy the timing requirement of
LCD panels.
24
www.ite.com.tw
IT986x V0.1.0
Function Description
0
1
2
3
4
5
6
0
1
2
3
4
5
6
DHCLK
(internal clock)
T1
T2
LCSN
T6
T3
LVSYNC
T5
T7
T4
LDEN
T8
LHSYNC,
LD[17:0]
Figure 5-4. 68-Type CPU Interface Timing
5.1.4
RGB with Serial Interface
The figure below illustrates the implementation for interfacing the IT986x family to an RGB with serial interface
LCM. IT986x family only supports one display for this interface.
IT986x family
Figure 5-5. Connection of IT986x Family to RGB with Serial Interface LCM
IT986x family supports 8/9/16 bits of serial interface to send the LCM command and uses 6/9/16/18/24 bits of
parallel RGB interface to send the display data. The timing for RGB with serial interface is shown in the following
figure.
25
www.ite.com.tw
IT986x V0.1.0
IT986x
LDCLK
T1
T3
LVSYNC
T2
T4
LHSYNC
LDEN
LD[23:0]
Invalid Data
Valid Data
LDCLK
LVSYNC
LHSYNC
T5
T6
LDEN
LD[23:0]
Invalid Data
Invalid
Data
Valid Data
Valid Data
Figure 5-6. RGB Timing (for data)
26
www.ite.com.tw
IT986x V0.1.0
Function Description
Figure 5-7. RGB Timing (for command)
5.1.5
RGB with Direct Control Interface
The figure below illustrates the implementation for interfacing the IT986x family to a RGB with direct control
interface LCM. IT986x family only supports one display with this interface
IT986x family
Figure 5-8. Connection of IT986x Family to RGB with Direct Control Interface LCM
Some LCMs do not have any serial interface, but only have parallel RGB interface. In this case, the unused pins
LCSN can be defined as GPIO. See Table 5-4 for detail. The timing for RGB parallel interface is shown in the
following figure.
27
www.ite.com.tw
IT986x V0.1.0
IT986x
LDCLK
T1
T3
LVSYNC
T2
T4
LHSYNC
LDEN
LD[23:0]
Invalid Data
Valid Data
LDCLK
LVSYNC
LHSYNC
T5
T6
LDEN
LD[23:0]
Invalid Data
Invalid
Data
Valid Data
Valid Data
Figure 5-9. RGB with Direct Control Interface Timing (for data)
5.1.6
CCIR601/656 Output Interface
IT986x family supports CCIR601/656 output interface. It can be connected to any device which has
CCIR601/656 input interface. The figure below illustrates the implementation. The CCIR601/656 output video
resolution and timing are programmable. It can be set to meet the system requirement. The general output
resolutions are 800x480, 640x480, 480x272, 320x240 and 240x320.
28
www.ite.com.tw
IT986x V0.1.0
Function Description
IT986x family
IT970 family
Host Processor
LVSYNC
LHSYNC
LDCLK
LD[7:0]
VSYNC
HSYNC
CLKIN
LD[7:0]
Figure 5-10. Connection of IT986x Family to Host Processor with CCIR601 Interface
IT986x family
IT970 family
Host Processor
LVSYNC
LHSYNC
LDCLK
LD[7:0]
CLKIN
LD[7:0]
Figure 5-11. Connection of IT986x Family to Host Processor with CCIR656 Interface
1 frame
LVSYNC
T1
T2
T4 (vertical active lines)
T3
LHSYNC
T6
LHSYNC
T5 (horizontal width)
T7
LDCLK
LD[7:0]
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Figure 5-12. CCIR601 Output Interface Timing
Table 5-5. CCIR601 Output Interface Timing Table
Symbol
Parameter
30 Frame/sec.
25 Frame/sec.
Unit
800x480 progressive video
T1
Vertical sync pulse width
8
8
line
T2
Vertical back porch
6
6
line
T3
Vertical front porch
6
6
line
T4
Vertical active lines
480
480
line
29
www.ite.com.tw
IT986x V0.1.0
IT986x
Symbol
Parameter
30 Frame/sec.
25 Frame/sec.
Unit
T5
Horizontal width of one active line
1600
1600
T (1)
T6
Horizontal sync pulse width
200
560
T
T7
Clock period
37 (2)
37
ns
640x480 progressive video
T1
Vertical sync pulse width
8
8
line
T2
Vertical back porch
6
6
line
T3
Vertical front porch
6
6
line
T4
Vertical active lines
480
480
line
T5
Horizontal width of one active line
1280
1280
T
T6
Horizontal sync pulse width
520
880
T
T7
Clock period
37
37
ns
480x272 progressive video
T1
Vertical sync pulse width
8
8
line
T2
Vertical back porch
10
10
line
T3
Vertical front porch
10
10
line
T4
Vertical active lines
272
272
line
T5
Horizontal width of one active line
960
960
T
T6
Horizontal sync pulse width
40
240
T
T7
Clock period
111(3)
111
ns
320x240 progressive video
T1
Vertical sync pulse width
20
20
line
T2
Vertical back porch
20
20
line
T3
Vertical front porch
20
20
line
T4
Vertical active lines
240
240
line
T5
Horizontal width of one active line
640
640
T
T6
Horizontal sync pulse width
110
260
T
T7
Clock period
148 (4)
148
ns
240x320 progressive video
T1
Vertical sync pulse width
15
15
line
T2
Vertical back porch
20
20
line
T3
Vertical front porch
20
20
line
T4
Vertical active lines
320
320
line
T5
Horizontal width of one active line
480
480
T
T6
Horizontal sync pulse width
120
240
T
T7
Clock period
148
148
ns
30
www.ite.com.tw
IT986x V0.1.0
Function Description
Notes:
1. T represents the clock period.
2. The clock frequency is 27.0 MHz.
3. The clock frequency is 9.0 MHz.
4. The clock frequency is 6.75 MHz.
1 frame
vertical blanking
lines
vertical active lines
T1
T2
Start of line
vertical blanking
lines
Next
line
Start of active line
T3
LDCLK
LD[7:0]
FF
00
00
XY
80
10
80
10
FF
00
00
XY
Y
Cb
Y
Cr
T4
EAV code
horizontal blanking
Y
Cb
Y
Cr
FF
T5
SAV code
horizontal width of one active line
Figure 5-13. CCIR656 Output Interface Timing
The SAV (start of active video) code and EAV (end of active video) code are embedded within the video data
stream. They replace the vertical sync and horizontal sync signals. The definitions of SAV and EAV codes are
shown in the following table.
Table 5-6. SAV Code and EAV Code
Bit Number
The 1st word
The 2nd word
The 3rd word
The 4th word
7 (MSB)
1
0
0
1
6
1
0
0
F(1)
5
1
0
0
V(2)
4
1
0
0
H(3)
3
1
0
0
P3(4)
2
1
0
0
P2
1
1
0
0
P1
0
1
0
0
P0
Notes:
1. When interleaved video: F = 0 for field 1 and F = 1 for field 2. When progressive video: F = 0.
31
www.ite.com.tw
IT986x V0.1.0
IT986x
2. V = 1 during vertical blanking, and V = 0 elsewhere.
3. H = 0 in SAV, H = 1 in EAV.
4. P3 ~ P0 are protection bits. Where P3 = V xor H, P2 = F xor H, P1 = F xor V, P0 = F xor V xor H.
Table 5-7. CCIR656 Output Interface Timing Table
Symbol
Parameter
30 frame/sec.
25 frame/sec.
Unit
800x480 progressive video
T1
Vertical blanking lines
20
20
line
T2
Vertical active lines
480
480
line
T3
Clock period
37 (2)
37
ns
T4
Horizontal blanking
192
552
T (1)
T5
Horizontal width of one active line
1600
1600
T
640x480 progressive video
T1
Vertical blanking lines
20
20
line
T2
Vertical active lines
480
480
line
T3
Clock period
37
37
ns
T4
Horizontal blanking
512
872
T
T5
Horizontal width of one active line
1280
1280
T
480x272 progressive video
T1
Vertical blanking lines
28
28
line
T2
Vertical active lines
272
272
line
T3
Clock period
111(3)
111
ns
T4
Horizontal blanking
32
232
T
T5
Horizontal width of one active line
960
960
T
320x240 progressive video
T1
Vertical blanking lines
60
60
line
T2
Vertical active lines
240
240
line
T3
Clock period
148 (4)
148
ns
T4
Horizontal blanking
102
252
T
T5
Horizontal width of one active line
640
640
T
240x320 progressive video
T1
Vertical blanking lines
55
55
line
T2
Vertical active lines
320
320
line
T3
Clock period
148
148
ns
T4
Horizontal blanking
112
232
T
T5
Horizontal width of one active line
480
480
T
32
www.ite.com.tw
IT986x V0.1.0
Function Description
Notes:
1. T represents the clock period.
2. The clock frequency is 27.0 MHz.
3. The clock frequency is 9.0 MHz.
4. The clock frequency is 6.75 MHz.
5.1.7
MIPI Output Interface
IT986x family supports MIPI output interface. The Figure 5-14 illustrates the implementation for interfacing with
MIPI Panel. The Line Levels in HS and LP Modes shown in the Figure 5-15. Figure 5-16 shows the sequence
of events during the transmission of a Data Burst.
IT986x family
Panel
MIPIDP3
MIPIDN3
MIPIDP2
MIPIDN2
MIPICKP
MIPICKN
MIPIDP1
MIPIDN1
MIPIDP0
MIPIDN0
DP3
DN3
DP2
DN2
CKP
CKN
DP1
DN1
DP0
DN0
Figure 5-14. Connection of IT986x Family to MIPI Panel
33
www.ite.com.tw
IT986x V0.1.0
IT986x
Figure 5-15. Line Levels in HS and LP Modes
Figure 5-16. High-Speed Data Transmission in Bursts
5.1.8
LVDS Interface
IT986x family supports LVDS interface, compliant with the JEIDA-24 and VESA-18, VESA-24 specifications.
5.1.8.1
JEIDA 24-bits
The Figure 5-17 illustrates the implementation for interfacing with JEIDA 24-bits LVDS panel. Figure 5-18 shows
the Interface Timing diagram.
Panel
IT986x family
LVDSP4
LVDSN4
LVDSP3
LVDSN3
LVDSP2
LVDSN2
LVDSP1
LVDSN1
LVDSP0
LVDSN0
RXIN3+
RXIN3RXCLK+
RXCLKRXIN2+
RXIN2RXIN1+
RXIN1RXIN0+
RXIN0-
Figure 5-17. Connection of IT986x Family to JEIDA 24-bits LVDS panel
34
www.ite.com.tw
IT986x V0.1.0
Function Description
Figure 5-18. JEIDA 24-bits Interface Timing
5.1.8.2
VESA 18-bits
The Figure 5-19 illustrates the implementation for interfacing with VESA 18-bits LVDS panel. Figure 5-20 shows
the Interface Timing diagram.
IT986x family
Panel
LVDSP3
LVDSN3
LVDSP2
LVDSN2
LVDSP1
LVDSN1
LVDSP0
LVDSN0
RXCLK+
RXCLKRXIN2+
RXIN2RXIN1+
RXIN1RXIN0+
RXIN0-
Figure 5-19. Connection of IT986x Family to VESA 18-bits LVDS panel
35
www.ite.com.tw
IT986x V0.1.0
IT986x
Figure 5-20. VESA 18-bits Interface Timing
5.1.8.3
VESA 24-bits
The Figure 5-21 illustrates the implementation for interfacing with VESA 24-bits LVDS panel. Figure 5-22 shows
the Interface Timing diagram.
IT986x family
Panel
LVDSP4
LVDSN4
LVDSP3
LVDSN3
LVDSP2
LVDSN2
LVDSP1
LVDSN1
LVDSP0
LVDSN0
RXIN3+
RXIN3RXCLK+
RXCLKRXIN2+
RXIN2RXIN1+
RXIN1RXIN0+
RXIN0-
Figure 5-21. Connection of IT986x Family to VESA 24-bits LVDS panel
36
www.ite.com.tw
IT986x V0.1.0
Function Description
Figure 5-22. VESA 24-bits Interface Timing
5.2
Host/Peripheral USB 2.0 Interface
This is a universal serial bus (USB) 2.0 On-The-Go (OTG) controller, which can play a dual role, either as a
host or as a peripheral controller. There are one USB controller. Host/Peripheral selectable. It controls with
USB_ID pin which it can be selected by any GPIO pins. When it acts as a host, it contains a USB host controller
that supports all-speed transactions. Without the software intervention, the host controller can deal with a
transaction-based data structure to offload the CPU and automatically transmit and receive data on the USB
bus. When it acts as a peripheral controller, each endpoint, except endpoint 0, accepts programmable HS/FS
transfer types to provide flexibility to suit all applications. In addition, complying with OTG standards means both
the Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) are supported. The system bus can
be a PVCI or AHB 32-bit bus interface. The transceiver interface is UTMI+ level 3, which supports the HS/FS/LS
transfers and a HS/FS hub.
Table 5-8. Dynamic Characteristics of DP/DM
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
300
-
-
mV
-50
-
500
mV
-
-
100
mV
Squelch is not detected.
150
-
-
mV
Disconnection is detected.
625
-
-
mV
-
-
525
mV
USB 2.0 transceiver (HS)
Input levels (Differential receiver)
VHSDIFF
High-speed
sensitivity
differential
input
|VI(DP) - VI(DM)|
Measured
at
connection
as
application circuit
VHSCM
Voltage range of high-speed data
signaling in the common mode
-
VHSSQ
High-speed
threshold
Squelch is detected.
VHSDSC
squelch
detection
High-speed
disconnection
detection threshold
the
an
Disconnection is not detected.
37
www.ite.com.tw
IT986x V0.1.0
IT986x
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
Output levels
VHSOI
High-speed
idle-level
voltage (Differential)
output
-
-10
-
10
mV
VHSOL
High-speed
low-level
voltage (Differential)
output
-
-10
-
10
mV
VHSOH
High-speed high-level
voltage (Differential)
output
-
-360
-
400
mV
VCHIRPJ
Chirp-J
output
(Differential)
voltage
-
700
-
1100
mV
VCHIRPK
Chirp-K
output
(Differential)
voltage
-
-900
-
-500
mV
40.5
45
49.5
Ω
3.0
-
3.6
V
|VI(DP) - VI(DM)|
0.2
-
-
V
-
0.8
-
2.5
V
0.8
-
2.0
V
Resistance
RDRV
Driver output impedance
Equivalent
resistance
used as the internal chip
Termination
VTERM
Termination voltage of the pull-up
resistor on the RPU pin.
-
USB 1.1 transceiver (FS/LS)
Input levels (Differential receiver)
VDI
Differential
sensitivity
VCM
Differential
voltage
input
voltage
common-mode
Input levels (single-ended receivers)
VSE
Single-ended receiver threshold
Output levels
VOL
Low-level output voltage
-
0
-
0.3
V
VHL
High-level output voltage
-
2.8
-
3.6
V
Min.
Typ.
Max.
Unit
Table 5-9. Static Characteristics of DP/DM
Symbol
Description
Conditions
Driver characteristics
High-speed mode
tHSR
High-speed differential rise time
-
500
-
-
ps
tHSF
High-speed differential fall time
-
500
-
-
ps
Full-speed mode
tFR
Rise time of DP/DM
CL = 50 pF; 10% ~ 90% of
|VOH - VOL|
4
-
20
ns
tFF
Fall time of DP/DM
CL = 50 pF; 90% ~ 10% of
|VOH - VOL|
4
-
20
ns
Differential rise/fall time matching
(tFR / tFF)
Excluding
the
first
transition from the idle
mode
90
-
110
%
tFRMA
38
www.ite.com.tw
IT986x V0.1.0
Function Description
Symbol
VCRS
Description
Output signal crossover voltage
Conditions
Min.
Typ.
Max.
Unit
Excluding
the
first
transition from the idle
mode
1.3
-
2.0
V
Low-speed mode
tLR
Rise time of DP/DM
CL = 200 pF ~ 600 pF;
10% ~ 90% of |VOH - VOL|
75
-
300
ns
tLF
Fall time of DP/DM
CL = 200 pF ~ 600 pF;
90% ~ 10% of |VOH - VOL|
75
-
300
ns
tLRMA
Differential rise/fall time matching
(tLR/tLF)
Excluding
the
first
transition from the idle
mode
80
-
125
%
VCRS
Output signal crossover voltage
Excluding
the
first
transition from the idle
mode
1.3
-
2.0
V
Driver timing
High-speed mode
Driver waveform requirement
Please refer to the eye
pattern of template 1
described
in
USB
specification, Rev. 2.0.
Follow template 1
Full-speed mode
Propagation delay
(VI, FSE 0, OE to DP, DN)
For
the
detailed
description of VI, FSE 0,
and OE, please refer to the
USB specification, Rev.
1.1.
-
-
15
ns
Low-speed mode
Not specified: The low-speed delay time is dominated by the slow tLR and tLF.
Receiver timing
High-speed mode (Template 4, USB 2.0 spec.)
Data source jitter and receiver
jitter tolerance
Please refer to the eye
pattern of template 4
described in the USB rev
2.0 specification.
Follow template 4
Full-speed mode
tPLH(rcv)
tPHL(rcv)
Receiver propagation delay (DP;
DM to RCV)
For
the
detailed
description of RCV, please
refer to the USB 1.1
specification.
-
-
15
ns
tPLH(single)
tPHL(single)
Receiver propagation delay (DP;
DM to VOP, VON)
-
-
-
15
ns
5.3
5.3.1
MMC/SD Interface
General Description
The IT986x family supports the MMC/SD card for users to store the audio files, JPEG image and MPEG-4
39
www.ite.com.tw
IT986x V0.1.0
IT986x
movies. It is convenient for users to put these data to the computer or download data from the computer. The
IT986x family is fully compliant with MMCA v4.3, and 8-bit data of MMCA v4.3.
5.3.2
MMC/SD Interface Timing Diagram
The MMC/SD Interface Timing diagram is shown in Figure 5-23. The detailed timing description is shown in
Table 5-10.
T9
T7
MMCCLK
T8
T2
T4
T1
MMCDAT
(Input)
MMCDAT
(Output)
T3
Data
Invalid Data
Data
Invalid
Data
Data
Data
T5
T6
Figure 5-23. MMC/SD Interface Timing Diagram
Table 5-10. MMC/SD Interface Timing Table
Symbol
Parameter
Min.
Max.
Units
T1
Input Hold Time
5
-
ns
T2
Clock fall time
-
10
ns
T3
Input Setup Time
5
-
ns
T4
Clock Rise Time
-
10
ns
T5
Output Hold Time
3
-
ns
T6
Output Setup Time
3
-
ns
T7
Clock High Time
10
-
ns
T8
Clock Low Time
10
-
ns
T9
Clock Cycle Time
40
-
ns
5.3.3
Multi SD Device Connection
5.3.3.1
Two SD card
Pin Name
GPIO13
GPIO15
GPIO16
GPIO17
GPIO18
GPIO14
SD0 Device
SD0_CMD
SD0_D0
SD0_D1
SD0_D2
SD0_D3
SD0_CLK
SD1 Device
SD1_CMD
SD1_D0
SD1_D1
SD1_D2
SD1_D3
40
www.ite.com.tw
IT986x V0.1.0
Function Description
Pin Name
GPIO11
5.3.3.2
5.4
SD0 Device
-
SD1 Device
SD1_CLK
SD card + SDIO
Pin Name
SD Device
SDIO Device
GPIO13
GPIO15
GPIO16
GPIO17
GPIO18
GPIO14
GPIO43
GPIO42
GPIO44
GPIO45
GPIO46
GPIO47
SD0_CMD
SD0_D0
SD0_D1
SD0_D2
SD0_D3
SD0_CLK
-
SD1_CMD
SD1_CLK
SD1_D0
SD1_D1
SD1_D2
SD1_D3
SPI Interface
Table 5-11. NOR Interface AC Timing
Symbol
Alt
Parameter
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
tCLCH
Serial Clock Fall Time (Slew Rate)
tCHCL
CS# Active Setup Time
tSLCH
tCSS
CS# Active Hold Time
tCHSH
CS# High Time
tSHSL
tCSH
Output Hold Time
tCLQX
tHO
Data In Setup Time
tDVCH
tDSU
Data In Hold Time
tCHDX
tDH
tV Output Valid from SCK
tCLQV
Notes: tCLH + tCLL must greater than 1 / FCLK
Fclk
tCH
tCL
Min.
D.C.
5.6
5.6
0.1
0.1
3
3
50
1
2
2
Typ.
Max.
80
6
Units
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
Figure 5-24. Serial Input Timing
41
www.ite.com.tw
IT986x V0.1.0
IT986x
Figure 5-25. Serial Output Timing
APB
REG_WR
SCLK_IN
REG_RD
APB Interface
ADDR[4:0]
Register Block
WDATA[31:0]
Serial Block
Generator
FS_IN
RDATA[31:0]
SSP_CLK_OE
SSP_FS_OE
TX_DMARQ
TX_DMAGNT
INT
RX_DMARQ
SCLK_O
Interrupt
Generator
RX_DMAGNT
SSP_CLK
TXFIFO
FS_O
Transmit /
Receive Control
Block
TXD
TXD_OE
RXD
RXFIFO
Figure 5-26. Block Diagram of NOR Interface
Table 5-12. Pin Share for AXISPI Interface
Pin Name
Mode 0
Mode 1
GPIO10
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
AXISPI_CLK
AXISPI_CS0
AXISPI_D0
AXISPI_D1
AXISPI_D2
AXISPI_D3
For the NOR booting, it only can connect GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 and GPIO10 to the NOR
device. The other pins are for the storage devices and without booting capability.
42
www.ite.com.tw
IT986x V0.1.0
Function Description
IT986x family
IT9852E/IT9856TE
NOR
SPI0 CSN
SPI0 DOUT
SPI0 DIN
SPI0 CLK
Hereunder is multi-chips connection to support two NORs. NOR1 is for the boot device while NOR2 is for the
storage device.
NOR 1
(bootable)
IT986x family
IT9852E/IT9856TE
SPI0 CSN #1
CSN
SPI0 CSN #2
SPI0 CLK
CLK
SPI0 DOUT
DI
SPI0 DIN
DO
NOR2 (storage)
CSN
CLK
DI
DO
5.5
5.5.1
Digital Audio Interface
General Description
IT986x family features a standard audio interface to support the transmission of mono or stereo data to and
from the DAC or ADC. The standard audio IT986x family support two data formats. One is standard IIS data
format and the other is left justified data format. IT986x family audio interface may be configured as either master
or slave. As a master interface mode, IT986x family generates the ACLK (ZCLK) and AWS (ZWS) and controls
sequencing of the data transfer. In the slave mode, DAC or ADC generates the ACLK (ZCLK) and AWS (ZWS)
and controls the sequencing of data transfer.
43
www.ite.com.tw
IT986x V0.1.0
IT986x
5.5.2
Digital Audio Interface Implementation
The audio interface in IT986x family has seven pins to support all the application implementation. The IT986x
family can connect one DAC and one ADC. IT986x family can be connected to CODAC as well, which depends
on the application’s purpose. There are three kinds of interface implementations, all of which can be configured
as either master or slave mode.
IT986x family
IT9852E/IT9856TE
CODEC
ZSDOUT
AMCLK
AWS
ACLK
ASDIN
5.5.3
Audio Interface Data Formats
IT986x family supports IIS and left justified audio interface data formats.
In IIS mode, The MSB is available on the second rising edge of ACLK following the AWS transition. The other
bits up to LSB are then transmitted in order. The figure below illustrates the IIS interface.
1/fs
Right Channel
Left Channel
AWS
ACLK
1 ACLK
ASDIN
1
2
MSB
1 ACLK
n-1 n
1
LSB
2
MSB
n-1 n
LSB
Figure 5-27. IIS Audio Interface
In Left justified mode, The MSB is available on the first rising edge of ACLK following the AWS transition. The
other bits up to LSB are then transmitted in order. The figure below illustrates the IIS interface.
44
www.ite.com.tw
IT986x V0.1.0
Function Description
1/fs
Right Channel
Left Channel
AWS
ACLK
1
ASDIN
2
n-1 n
MSB
1
LSB
2
n-1 n
MS
B
LSB
Figure 5-28. MSB Left Justified Interface
5.6
UART and IrDA Interface
The UART and IrDA controller is a serial communication element that implements the most common infrared
communication protocols. In addition to the infrared modes, the device also provides the operation in the UART
mode, which is backward compatible to 16550 to support the existing communication software.
It provides the following features:
5.7
Firmware compatible with the high-speed NS 16C550A UART
IrDA 1.3 SIR with up to 115.2 kbps data rate
SIR pulse width programmable as 1.6 μs or 3/16 of the baud-rate pulse width
Supports IrDA 1.3 FIR
Multi-frame transmission and reception in FIR mode
Back-to-back infrared frame transmission and reception in FIR mode
32-bit IEEE 802 CRC32 hardware CRC generators and checkers for FIR communications
Break, parity, overrun, and framing error simulations in UART mode
CRC error and physical error simulation in FIR mode
DMA Controller
IT986x family’s Direct Memory Access controller is designed to enhance the system performance and reduce
processor-interrupt generation. The system efficiency is improved by employing high-speed data transfer
between the system and device. The DMA controller provides 8 channels for memory-to-memory, memory-toperipheral, and peripheral-to-memory transfer with a shared buffer.
Here are the main features:
5.8
An AHB slave port for DMA controller configuration
2 AHB master interfaces for data transfer
8 configurable DMA channels
Supports chain transfer
Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers
Group round-robin arbitration scheme with 4 priority levels
Supports 8-, 16-, and 32-bit wide data transaction
Supports big-endian and little-endian
Ethernet MAC Interface
45
www.ite.com.tw
IT986x V0.1.0
IT986x
The IT986x family provides a high-quality 10/100 Ethernet controller with DMA function. It includes an AHB
wrapper, DMA engine, on-chip memories (TX FIFO and RX FIFO), MAC, and RMII interface. It is an Ethernet
controller that provides AHB master capability and is fully compliant with the IEEE 802.3 100 Mbps and 10 Mbps
specifications. The MAC DMA controller handles all data transfers between the system memory and on-chip
memories. The DMA engine supports the zero-copy data transfer that drastically improves the system
performance. The DMA engine can be used to reduce the CPU loading, maximize the performance, and
minimize the FIFO size. It has on-chip memories for buffering, which does not require the external local buffer
memory. The RMII interface can support two specific data rates, 10 Mbps and 100 Mbps. The functionality is
identical at both data rates, and so is the signal timing relationship. The only difference between the 10 Mbps
and 100 Mbps operations is the nominal clock frequency.
5.9
PLL Interface
IT986x family has three clock synthesizers to generate all of the internal clocks. The clock synthesizer can
generate a wide range of programmable frequencies up to 1GHz. The clock synthesizer accepts 12 MHz
reference clock input. Moreover, the system can even stop the reference clock after the PLL locks the target
frequency and phase for power saving.
5.10
2D Graphice Engine
The 2D Graphics Accelerator supports the following functions:
5.11
Bit Block Transfer (BitBlt) with ROP3 operation
Mask plane with 1bpp, 2bpp, 4bpp, and 8bpp format
Color expansion with 1bpp, 2bpp, 4bpp and 8bpp format
Constant/Variable global alpha blending
Coordinate transform
Gradient (horizontal / vertical) fill with dithering / solid color fill
Clipping window
Supports following color formats:
32-bit ARGB8888, ABGR8888, RGBA8888, and BGRA8888
16-bit ARGB4444, ABGR4444, RGBA4444, BGRA4444, ARGB1555, ABGR1555, RGBA1555, and
BGRA1555
16-bit RGB565, and BGR565
Alpha A_8, A_4, A_2, and 1-bit black and white BW_1
Color depth conversion from any to any RGB format with dithering
Supports interrupt output
64-bit memory interface with maximum 4-pixel pipelined engine
Up to 4096x4096 pixels display resolution
Automatic clock gating
JPEG
The IT986x family’s JPEG codec is based on the JPEG baseline standard and the arithmetic accuracy meets
the requirement of the compatibility test of JPEG Part-2 (ISO/IEC10918-2). The maximum image size is 256M
pixels (16376x16376). The parameters in the luminance and chrominance quantization table are fully
programmable. The Huffman table is the default one suggested by the specification. The decoding process
supports YUV 4:4:4, 4:2:2, 4:1:1 and 4:2:0 with the interleaved format, but the encoding process only supports
the YUV 4:2:2 with the interleaved format. The progressive mode is not supported, while the sequential mode
is supported.
5.12
Video
Supports H.264 decoding, which meets high/main profile level 3.1 and decodes 1080p@30fps (1920x1080) in
real time.
46
www.ite.com.tw
IT986x V0.1.0
Function Description
5.13
SAR ADC
It is an 8-channel analog-to-digital converter which supports sampling rate of 1 Mhz with 12 bits resolution.
5.14
General-Purpose I/O
The GPIO controller is a user programmable general-purpose I/O controller. It is used to input/output data from
the system and device. Each GPIO can be programmed as the input or output and pulled high or pulled low.
This GPIO can also be an interrupt input. It supports the rising edge, falling edge, both edge, and high/low level
interrupt sense types. Each port can choose the pre-scale APB clock source as an interrupt source.
All GPIO pins are set to input upon the hardware reset.
47
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
48
www.ite.com.tw
IT986x V0.1.0
DC Characteristics
6. DC Characteristics
Absolute Maximum Ratings*
Core Power (VDD_CORE) ................ -0.3V to 2.0V
*Comments
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to this device. These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied or intended. Exposure to the absolute
maximum rating conditions for extended periods
may affect device reliability.
IO Power (VDD_IO) ......................... -0.3V to 4.0V
Input Voltage (Vi) ............. -0.3V to VDD_IO + 10%
Output Voltage (Vo) ......... -0.3V to VDD_IO + 10%
Operation Temperature (Topt) ....... -40C to +85C
Storage Temperature .................. -55C to +125C
Normal Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD_CORE
Core Power (IVDD) – CPU
0.99
1.1
1.21
V
VDD_MEM
DDR2 Memory Power (IT9862, IT9866)
1.7
1.8
1.9
V
VDD_MEM
DDR3 Memory Power (IT9868)
1.35
1.5
1.65
V
VDD_IOA
VDD_IOB
I/O Power
3.0
3.3
3.6
V
VDD_RTC
RTC Power
2.0
3.3
3.6
V
VDD_PLL
OSC Power
0.99
1.1
1.21
V
VDD_USB
USB Power
2.0
3.3
3.6
V
+85
0
-
Operating Temperature
-40
-
C
DC Electrical Characteristics
49
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
50
www.ite.com.tw
IT986x V0.1.0
AC Characteristics
7. AC Characteristics
7.1
Reset Timing
VDD_IOA
VDD_IOB
T2
T2
VDD_CORE
VDD_MEM
T1
T3
T1
RSTN
Figure 7-1. Reset Timing
Table 7-1. Reset Timing Table
Symbol
Parameter
Min.
Typ.
Max.
Unit
T1
Core Power (memory power) valid to reset inactive
-
50
-
ms
T2
I/O Power valid to reset inactive
-
40
-
ms
T3
Minimum reset pulse width
1
-
-
ms
Min.
Typ.
Max.
Unit
10
-
-
us
Notes: The registers can be accessed 4 ms after the reset process is finished.
7.2
Power Sequence
Specific sequencing requirements shall be followed for all I/O power and core power
Figure 7-2. Power Sequence Timing
Table 7-2. Power Sequence Table
Symbol
T1
Parameter
Core power (memory power) valid to I/O power valid
51
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
52
www.ite.com.tw
IT986x V0.1.0
Package Information
8. Package Information
8.1
IT986x Family Package Information
E3
LQFP 128(14*14) Outline Dimensions for IT9862, IT9866, and IT9868
unit: inches/mm
D3
C
0.8
Symbol
Dimensions in inches
Dimensions in mm
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
0.063
-
-
1.60
A1
0.002
-
0.006
0.05
-
0.15
A2
0.053
0.055
0.057
1.35
1.40
1.45
b
0.005
0.006
0.009
0.13
0.16
0.23
c
0.004
-
0.008
0.09
-
0.20
D/E
0.630 BSC
16.00 BSC
D1 / E1
0.551 BSC
14.00 BSC
D3 / E3
0.270
e
L
0.278
6.86
0.016 BSC
0.018
L1
0.274
0.024
-
7.06
0.40 BSC
0.030
0.45
0.039 REF.
0°
6.96
0.60
0.75
1.0 REF.
7°
0°
-
7°
Notes:
1.
Dimensions D1 and E1 do not include mold protrusion, but mold mismatch is included.
2.
Dimensions b does not include dambar protrusion.
3.
Controlling dimensions: Millimeter
DI-E(274*274MIL)-LQFP128(14*14)v0
53
www.ite.com.tw
IT986x V0.1.0
IT986x
This page is intentionally left blank.
54
www.ite.com.tw
IT986x V0.1.0
Ordering Information
9. Ordering Information
Part Number
Description
IT9862E/AW
Application Processor SoC
IT9866E/AW
Application Processor SoC With H.264 Decoder
IT9868E/AW
Application Processor SoC With H.264 Decoder
Package
128 pins
LQFP/EPAD
128 pins
LQFP/EPAD
128 pins
LQFP/EPAD
Body
Size
14*14
mm
14*14
mm
14*14
mm
All green components provided are in compliance with RoHS, and Halogen-Free.
55
www.ite.com.tw
IT986x V0.1.0
工商网监
湘ICP备2023018690号
