IX4351NE
9A Low Side
SiC MOSFET & IGBT Driver
INTEGRATED CIRCUITS DIVISION
Features
Description
• Separate 9A peak source and sink outputs
• Operating Voltage Range: -10V to +25V
• Internal charge pump regulator for selectable
negative gate drive bias
• Desaturation detection with soft shutdown sink driver
• TTL and CMOS compatible input
• Under Voltage lockout (UVLO)
• Thermal shutdown
• Open drain FAULT output
The IX4351NE gate driver is designed specifically to
drive SiC MOSFETs and high power IGBTs. Separate
9A source and sink outputs allow for tailored turn-on
and turn-off timing while minimizing switching losses.
An internal negative charge regulator provides a
selectable negative gate drive bias for improved dV/dt
immunity and faster turn-off.
Applications
•
•
•
•
•
On-board chargers
DC-DC converters
Electric vehicle charging stations
Motor controllers
Power inverters
Desaturation detection circuitry senses an over
current condition of the SiC MOSFET and initiates a
soft turn off, thus preventing a potentially damaging
dV/dt event. The non-inverting logic input, IN, is TTL
and CMOS compatible; internal level shifters provide
the necessary bias to accommodate negative gate
drive bias voltages. Additional protection features
include UVLO detection and thermal shutdown. An
open drain FAULT output signals a fault condition to
the microcontroller.
IX4351NE Functional Block Diagram
The IX4351NE is available in a thermally enhanced
16-pin narrow SOIC package.
VDD
IN
6
Gate and
Control
Logic
5
DESAT
2
3
VDD
VDD
1
OUTSRC
16
OUTSNK
15
10
VSS
VSS
14
OUTSOFT
13
INSOFT
12
CAP
11
GND
7
COM
Ordering Information
6.8V
RIN
FAULT
4
Part
Description
IX4351NE
16-Pin narrow SOIC with exposed thermal
pad. In tubes (50/Tube)
IX4351NETR
16-Pin narrow SOIC with exposed thermal
pad. In Tape & Reel (2000/Reel)
VDD
VSS
VREG
8
4.6V
Regulator
2.6V
VDD
SET
9
DS-IX4351NE-R03
Charge
Pump
Control
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1
IX4351NE
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
4
4
6
2. Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Logic Input (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Gate Drive Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Internal 4.6V Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Negative Supply Voltage (VSS) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Desaturation Detection and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 DESAT Input Component Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 DESAT Blanking Time Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.10 FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
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13
13
13
13
14
R03
IX4351NE
INTEGRATED CIRCUITS DIVISION
1 Specifications
1.1 Package Pinout
IX4351NE
OUTSRC 1
16 OUTSNK
VDD 2
15 VSS
VDD 3
14 OUTSOFT
DESAT 4
13 INSOFT
FAULT 5
12 CAP
IN 6
11 GND
COM 7
10 VSS
VREG 8
9 SET
Bottom Side
Thermal Pad
1.2 Pin Description
R03
Pin#
Name
Pin Type
Description
1
OUTSRC
Output
Gate driver, source
2, 3
VDD
Power
Positive supply voltage: Connect pin 2 to pin 3 on printed circuit board (PCB)
4
DESAT
Input
Sense input for desaturation detection
5
FAULT
Output
Fault status, Open-Drain, active low.
6
IN
Input
Logic input
7
COM
Power
Common ground connection: Connect to GND
8
VREG
Output
4.6V regulator output
9
SET
Input
Sets negative supply voltage (VSS) level
10, 15
VSS
Power
Negative supply voltage: Connect pin 10 to pin 15 on the PCB
11
GND
Power
Charge pump ground connection: Connect to COM
12
CAP
Output
Charge pump output
13
INSOFT
Input
Soft Shutdown sense input
14
OUTSOFT
Output
Soft Shutdown - Gate driver, sink
16
OUTSNK
Output
Gate driver, sink
-
Thermal Pad
Thermal
Must be connected to VSS or left floating.
Do not connect to any other signal or net.
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3
IX4351NE
INTEGRATED CIRCUITS DIVISION
1.3 Absolute Maximum Ratings
Unless otherwise specified all voltages are with respect to VCOM and electrical ratings are over the operational
ambient temperature range.
Parameter
Symbol
Minimum
Maximum
Units
Positive Supply Voltage
VDD
-0.3
32
V
Negative Supply Voltage
VSS
-10
0
V
VDD - VSS
-0.3
40
V
V
Supply Voltage Range
VGND
-0.3
+0.3
Gate Drive Output Voltages
VOUTSRC , VOUTSNK , VOUTSOFT
VSS - 0.3
VDD + 0.3
V
Gate Drive Output Current
IOUTSRC , IOUTSNK
-
±9
AP
VIN
-0.3
7
V
VDESAT
-0.3
VDD + 0.3
V
SET Input Voltage
VSET
-1
7
V
FAULT Output Voltage
VFAULT
-0.3
VDD + 0.3
V
VREG Output Voltage
VREG
-0.3
7
V
Junction Temperature
TJ
-55
+150
°C
Storage Temperature
TSTG
-55
+150
°C
Ground Separation
IN Input Voltage
DESAT Input Voltage
1.4 Recommended Operating Conditions
Parameter
Symbol
Minimum
Maximum
Units
Positive Supply Voltage
VDD
13
25
V
Negative Supply Voltage
VSS
-3.5
-10
V
Input Voltage
VIN
0
5.5
V
Operating Ambient Temperature
TA
-40
125
°C
1.5 Electrical Characteristics
Unless otherwise specified, electrical characteristics are guaranteed at: VDD=20V, VSS=-5V, COM=GND=0V,
VINH=5V, VINL=0V, CDD=CREG=4.7F, CSS=10F, and -40°C < TA < +125°C.
1.5.1 VDD
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
Operating VDD Supply Current
fIN=100kHz, VSET=0.4V,
CLOAD=2.2nF
IDD
-
19
28
mA
Quiescent VDD Supply Current
VIN=0V, VSET=-0.4V, No load
IDDQ
-
2.9
4.4
mA
VDD UVLO Rising Threshold
-
VDDUV+
10
12
13
V
VDD UVLO Hysteresis
-
VDDHYS
-
2
-
V
4
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R03
IX4351NE
INTEGRATED CIRCUITS DIVISION
1.5.2 VREG
Parameter
Regulator Output Voltage
Conditions
Symbol
Minimum
Typical
Maximum
Units
IREG=-5mA
VREG
4.2
4.6
5
V
-
0.1
0.2
V
-
0.1
0.4
V
Line Regulation
15V < VDD < 25V, IREG=-5mA
Load Regulation
-1mA < IREG < -10mA
VREG
1.5.3 Charge Pump and VSS
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
-
VSS
-3.5
-
-8
V
CFLY=68nF, RFLY=33
ISS
-
-
50
mA
VSET = -0.4V
fOSC
90
124
160
kHz
Conditions
Symbol
Minimum
Typical
Maximum
Units
VDESAT=0V
IDESAT
400
570
750
A
-
VDESAT,TH
6
6.8
8
V
CBLANK=0F
tBLANK
-
250
-
ns
-
RDST(on)
-
900
-
Conditions
Symbol
Minimum
Typical
Maximum
Units
-
TSD
-
160
-
°C
-
TSDHYS
-
20
-
°C
Conditions
Symbol
Minimum
Typical
Maximum
Units
High Level Logic Input Voltage
-
VINH
2.2
-
-
V
Low Level Logic Input Voltage
-
VINL
-
-
1
V
Input Voltage Hysteresis
-
VINHYS
0.2
0.4
-
V
High Level Input Current
VIN=5V
IINH
-
50
70
A
Low Level Input Current
VIN=0V
IINL
-
-
-10
A
Input Pull-Down Resistance
VIN=5V
RIN
-
100
-
k
Conditions
Symbol
Minimum
Typical
Maximum
Units
Output Low Voltage
IFAULT=20mA
VFAULTL
-
-
0.8
V
Output Leakage Current
VFAULT=20V
IFAULT
-
0.1
10
A
-
tFAULTDLY
-
150
-
ns
Negative Supply Voltage Range
Average VSS Current
Charge Pump Frequency
1.5.4 Desaturation
Parameter
DESAT Source Current
DESAT Detect Threshold Voltage
Blanking Time
DESAT Pull Down On-Resistance
1.5.5 Thermal Shutdown
Parameter
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1.5.6 IN
Parameter
1.5.7 FAULT
Parameter
DESAT Detect to FAULT Propagation Delay
R03
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5
IX4351NE
INTEGRATED CIRCUITS DIVISION
1.5.8 Soft Shutdown
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
Soft Shutdown Threshold Voltage
-
VINSOFT,TH
2.3
2.6
3
V
Soft Shutdown Hysteresis
-
VINSOFTHYS
-
0.4
-
V
OUTSOFT Peak Sink Current
-
IOUTSOFT
-
900
-
mA
IOUTSOFT=100mA
ROUTSOFT
-
6
15
-
tOUTSOFTDLY
-
125
-
ns
Conditions
Symbol
Minimum
Typical
Maximum
Units
High Level Output Voltage
IOUTSRC=-100mA
VOUTSRC
VDD- 0.25
-
-
V
Low Level Output Voltage
IOUTSNK=100mA
VOUTSNK
-
-
0.25
V
OUTSRC On-Resistance
IOUTSRC=-100mA
ROUTSRC
-
1.16
2
OUTSNK On-Resistance
IOUTSNK=100mA
ROUTSNK
-
0.8
1.5
Turn-On Propagation Delay Time
CLOAD=1nF
tON
-
75
125
ns
Turn-Off Propagation Delay Time
CLOAD=1nF
tOFF
-
65
125
ns
Turn-On Rise Time
CLOAD=1nF
tR
-
10
20
ns
Turn-Off Fall Time
CLOAD=1nF
tF
-
10
20
ns
OUTSOFT On-Resistance
DESAT Detect to OUTSOFT Propagation Delay
1.5.9 Gate Drive Output
Parameter
1.6 Thermal Characteristics
Parameter
Symbol
Rating
Units
Thermal Impedance, Junction to Ambient
JA
60
°C/W
Thermal Impedance, Junction to Case
JC
28
°C/W
6
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R03
IX4351NE
INTEGRATED CIRCUITS DIVISION
2 Performance Data
Unless otherwise noted VDD=20V, TA=25°C, and values are typical.
IN Logic Threshold
vs. VDD Supply Voltage
IN Logic Threshold vs. Temperature
VINL
-50
-25
0
25
50
75 100
Temperature, TA (ºC)
125
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VINH
VINL
700
650
600
550
500
450
400
0
25
50
75 100
Temperature, TA (ºC)
125
15
20
25
Supply Voltage VDD (V)
100
75
50
25
0
-50
150
-25
0
25
50
75 100
Temperature, TA (ºC)
30
CL=3.3nF
20
CL=1nF
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
24
CL=1nF
0
25
50
75 100
Temperature, TA (ºC)
125
150
150
145
140
135
14
26
-25
DESAT Detect to FAULT Delay
vs. Temperature
155
CL=3.3nF
20
16
18
20
22
Supply Voltage VDD (V)
Supply Current IDD vs. Temperature
(CFLY=68nF, IN: =1kHz, 0-5V,
50% Duty Cycle, CL=1nF)
120
Supply Current IDD (mA)
Supply Current IDD (mA)
18
20
22
Supply Voltage VDD (V)
0
160
0
16
25
CL=6.8nF
30
0
150
50
CL=10nF
10
10
125
75
-50
Delay (ns)
Fall Time (ns)
CL=6.8nF
25
50
75 100
Temperature, TA (ºC)
165
40
40
0
100
150
50
CL=10nF
Rise Time (ns)
125
-25
125
Turn-Off Fall Time vs. Supply Voltage
50
VDD=25V
VDD=20V
VDD=15V
24
26
-50
-25
0
25
50
75 100
Temperature, TA (ºC)
125
150
Supply Current IDD vs. IN Frequency
(CL=1nF, VSS= -4.7V)
VDD=25V
VDD=20V
VDD=15V
100
80
60
40
20
0
-50
R03
-50
Turn-Off Propagation Delay Time
vs. Temperature
125
Turn-On Rise Time vs. Supply Voltage
14
6.5
30
Turn-Off Propagation Delay (ns)
Turn-On Propagation Delay (ns)
DESAT Current (A)
750
-25
DESAT Falling Threshold
Turn-On Propagation Delay Time
vs. Temperature
DESAT Current vs. Temperature
-50
DESAT Rising Threshold
7.0
6.0
10
150
DESAT Threshold vs. Temperature
7.5
DESAT Threshold (V)
VINH
IN Logic Threshold (V)
IN Logic Threshold (V)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
-25
0
25
50
75 100
Temperature, TA (ºC)
125
150
0
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500
1000
1500
IN Frequency (kHz)
2000
7
IX4351NE
INTEGRATED CIRCUITS DIVISION
OUTSRC On-Resistance
vs. Supply Voltage
OUTSNK On-Resistance
vs. Supply Voltage
OUTSOFT On-Resistance
vs. Supply Voltage
0.90
1.35
6.5
1.25
1.20
1.15
On-Resistance ()
On-Resistance ()
On-Resistance ()
6.4
1.30
0.85
0.80
6.3
6.2
6.1
6.0
5.9
5.8
0.75
1.10
14
8
16
18
20
22
Supply Voltage VDD (V)
24
26
5.7
14
16
18
20
22
Supply Voltage VDD (V)
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24
26
14
16
18
20
22
Supply Voltage VDD (V)
24
26
R03
IX4351NE
INTEGRATED CIRCUITS DIVISION
3 Functional Description
The IX4351NE is designed to provide the gate drive for high power SiC MOSFETs and IGBTs.
Figure 1. IX4351NE Typical Application Circuit
IX4351NE
IN
4
6
6.8V
RIN
Controller
VDD
D1
LOAD
CBLANK
2
VDD
3
V+
RDESAT
DESAT
+22V
DRAIN
CDD
Gate and
Control
Logic
FAULT
5
1
16
RH
OUTSRC
GATE
OUTSNK
RL
SOURCE
VSS
INSOFT
13
2.6V
VDD
14
VREG
8
4.6V
Regulator
10
CREG
VDD
R1
SET
9
RSOFT
OUTSOFT
VSS
15
Charge
Pump
Control
12
CAP
RFLY
CFLY
CSS
11
R2
GND
COM
7
VSS
3.1 Power Supplies
The IX4351NE requires only a single positive supply
(VDD) to provide SiC and IGBT gate driver functionality
by generating the negative voltage (VSS) required to
efficiently turn off SiC and IGBT power switches. VDD
provides the supply voltage for the gate driver outputs,
the charge pump output driver and the internal low
voltage regulator. An on-board regulator provides a
low voltage supply (VREG) used by the internal control
logic while the on-board charge pump generates the
pulses necessary to create the negative voltage
supply (VSS).
3.2 Logic Input (IN)
IN, the gate driver logic input, is a TTL and CMOS
logic level compatible high-speed Schmitt trigger
buffer that controls the gate driver outputs: OUTSRC,
OUTSNK, and OUTSOFT. The input voltage logic
thresholds have 0.4V of hysteresis and are referenced
R03
to COM. On startup, after VDD and VSS reach their
minimum operating voltage levels by exceeding their
Under Voltage Lock Out thresholds, IN controls the
state of the gate driver outputs according to the table
below:
Table 1: IN Gate Control Truth Table
IN
OUTSRC
OUTSNK
OUTSOFT
0
1
Off
High
Low
Off
Low
Off
3.3 Gate Drive Outputs
The IX4351NE has three gate drive outputs. Two
power outputs, OUTSRC and OUTSNK, are rated for
9A peak current while the third output, OUTSOFT, is
rated for 900mA peak current. Separate source and
sink high current outputs allow independent
adjustment of the discrete power SiC MOSFET or
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9
IX4351NE
INTEGRATED CIRCUITS DIVISION
IGBT turn-on and turn-off transactions by means of a
single resistor for each output. An internal
non-adjustable dead time prevents cross conduction
of the source and sink outputs.
During normal operation whenever IN, the gate control
input, is driven to a logic low the lower rated current
sink output, OUTSOFT, turns on concurrently with
OUTSNK. These operations can be seen in Figure 2,
“Timing Diagram,” on page 11. In the timing diagram
these normal operation transactions can be seen with
the first cycle of the IN waveform.
3.4 Internal 4.6V Regulator (VREG)
The internal 4.6V regulator provides power for the
internal low voltage control circuitry and requires an
external 4.7F bypass capacitor (CREG). Capable of
sourcing up to 10mA, VREG is utilized to set the
negative supply voltage level and optionally power the
LED of an external optocoupler.
3.5 Negative Supply Voltage (VSS) Generation
The IX4351NE inverting charge pump regulator
circuitry outputs VSS, a regulated negative supply
voltage. Operating in a closed-loop mode the charge
pump generates VSS from VDD with regulation being
achieved by sensing the VSS voltage with respect to
VREG at the SET input by means of the resistor divider
R1 and R2. See Figure 1, “IX4351NE Typical
Application Circuit,” on page 9 for the circuit
configuration. The charge pump inverter requires two
discrete Schottky diodes, two external ceramic
capacitors, and a peak output current limiting resistor
(RFLY). VSS is set by the R1 and R2 resistor divider
given in the following equation:
R2
V SS = – V REG -------
R1
Where R1 + R2 ~ 100k
The recommended value of the charge pump inverter
components is:
1. RFLY = 33
2. CFLY = 68nF
3. CSS = 10uF
To prevent damaging the charge pump output, CAP,
the value of RFLY must not be reduced.
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3.6 Desaturation Detection and Protection
DESAT detection occurs when the SiC or IGBT power
transistor goes into an over-current condition causing
the voltage across the transistor to exceed a
predetermined threshold chosen by the designer.
The desaturation protection circuit ensures the safety
of the external SiC MOSFET or IGBT during turn-off
whenever the power switch is in an over-current
situation. The DESAT pin monitors the drain voltage of
the power SiC MOSFET or the collector of the power
IGBT via the input circuitry between the DESAT input
and the SiC MOSFET drain or the IGBT collector.
When the sum of the drain or collector voltage plus the
voltage drop of the DESAT input circuitry exceeds the
DESAT Threshold Voltage (VDESAT,TH), typically 6.8V,
the FAULT output goes low, the internal MUTE
function is activated and a controlled turn-off
sequence is initiated. OUTSRC is turned off and
OUTSOFT is turned on. The OUTSOFT 900mA sink
capability provides an initial slow turn-off of the
external SiC MOSFET or IGBT. When the GATE
voltage decreases to the Soft Shutdown Threshold
Voltage (VINSOFT,TH), typically 2.6V, OUTSNK turns
on and quickly pulls the GATE to VSS. This two-step
turn-off avoids dangerous dV/dt transient over-voltage
spikes across the external SiC MOSFET or IGBT.
When DESAT is detected the MUTE feature is
activated. MUTE holds FAULT low and masks logic
inputs applied to IN for a nominal duration of 2ms.
Once the MUTE timer expires, FAULT is released and
the input will begin normal operation with the next low
to high transition of IN.
The DESAT detection and two-step turn-off sequence
can be seen in Figure 2, “Timing Diagram,” on
page 11. In the timing diagram, this sequence begins
with the second rising edge of IN.
To avoid a false desaturation detect event during
turn-on of the external SiC MOSFET or IGBT, the
IX4351 provides a nominal 250ns DESAT detect
blanking time (tBLANK) beginning when OUTSRC
transitions from OFF to ON causing the gate drive
output voltage to rise. While OUTSRC is off, the
DESAT input is internally pulled low. To accomplish
the fixed internal blanking time and to precondition the
DESAT input for the fully turned on SiC MOSFET or
IGBT, the DESAT input internal pull down remains
active for the duration of the blanking period.
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IX4351NE
INTEGRATED CIRCUITS DIVISION
Although the nominal internal blanking duration is
fixed at 250ns it can be extended by means of an
external capacitor, CBLANK, installed from the DESAT
input to COM. Once the internal pull down is released,
the additional blanking duration is set by the time it
takes to charge the total external capacitive loading of
the DESAT input up to VDESAT,TH. The value of
CBLANK is the difference between the total
capacitance required to obtain the desired blanking
period less the capacitive loading of the other
components on DESAT.
Figure 2. Timing Diagram
IN
VDD
Hi-Z
OUTSRC
Hi-Z
OUTSNK
VSS
Hi-Z
VINSOFT,TH
OUTSOFT VSS
VDESAT,TH
DESAT
Hi-Z
FAULT
tON
tOFF
tOUTSOFTDLY
tBLANK
MUTE
3.7 DESAT Input Component Selection
The value of RDESAT is determined by the peak surge
current permitted through diode D1 and the maximum
voltage across the external power transistor. When IN
is high and the power SiC MOSFET is on, the voltage
at the DESAT input is calculated by the following
equation.
V DESAT = I DESAT R DESAT + V f + V DS
Substitute VCE for VDS when using an IGBT.
where Vf is the forward voltage drop of D1.
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For a desired drain-to-source voltage (VDS,TH), the
desaturation detect threshold equation is:
V DESAT TH – V DS TH = I DESAT R DESAT + nV f
Substitute VCE,TH for VDS,TH when using an IGBT.
where “n” is the number of series diodes in the DESAT
detection input circuit.
Using multiple series diodes improves DESAT
detection consistency by minimizing RDESAT. Larger
values of RDESAT lessens DESAT detection uniformity
due to variations of IDESAT. This of course assumes
the diode is operating above its forward bias knee
voltage with a forward current of IDESAT.
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IX4351NE
INTEGRATED CIRCUITS DIVISION
3.8 DESAT Blanking Time Stretching
3.10 FAULT Output
Extending the blanking period is easily accomplished
by the addition of an external capacitor to the DESAT
input. Blanking time extension is the difference
between the nominal 250ns fixed internal blanking
period and the required total blanking time of the
design.The equation for the total blanking time is given
in the following equation.
The FAULT output indicates the IX4351NE is
undergoing a fault condition. The open-drain NMOS
output pulls low whenever one of the four monitored
fault conditions is detected. They are:
V DESAT TH C TOTAL
t TOTAL = 250ns + ---------------------------------------------------I DESAT
Where CTOTAL is the total external capacitance seen
by the DESAT input pin. For the design example
shown in Figure 1, “IX4351NE Typical Application
Circuit,” on page 9, CTOTAL is the sum of CBLANK and
CJ, the junction capacitance of D1. CBLANK is
calculated as follows:
C BLANK
t TOTAL – 250ns I DESAT C J
= ----------------------------------------------------------------- – -----V DESAT TH
n
Where “n” is the number of series diodes in the
DESAT detection input circuit.
Optionally the total capacitance may include the
junction capacitance of a protection zener diode from
DESAT to COM. Because this additional junction
capacitance is added to CTOTAL it reduces the
calculated value of CBLANK.
3.9 Thermal Shutdown
Thermal protection circuity pulls FAULT low, turns off
OUTSRC, turns on both OUTSNK and OUTSOFT,
and disables the charge pump whenever the
IX4351NE internal junction temperature reaches a
nominal +160°C. After the internal junction
temperature decreases by approximately 20°C the
device returns to normal operation.
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1. VDD Under Voltage Lock Out.
FAULT output goes low until VDD UVLO clears.
OUTSRC is turned off.
OUTSNK and OUTSOFT go low.
Charge pump disabled.
2. VSS Under Voltage Lock Out.
FAULT output goes low until VSS UVLO clears.
OUTSRC is turned off.
OUTSNK and OUTSOFT go low.
Charge pump continues running.
3. DESAT detection.
FAULT output goes low for a nominal 2ms.
OUTSRC is turned off.
OUTSOFT goes low.
Gate voltage crosses VINSOFT,TH
OUTSNK goes low.
Charge pump unaffected.
4. Thermal Shut Down.
FAULT output goes low until TSD clears.
OUTSRC is turned off.
OUTSNK and OUTSOFT go low.
Charge pump disabled.
When the UVLO and TSD faults clear, the IX4351NE
returns to normal operation and the gate driver
outputs immediately transition to comply with the
current IN logic state.
When the DESAT fault clears, the FAULT output
remains low until the 2ms MUTE timer expires. The
gate drive outputs remain low until the next low to high
IN transition after the MUTE timer expires.
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IX4351NE
INTEGRATED CIRCUITS DIVISION
4 Manufacturing Information
4.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of
the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all
of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our
devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Classification
IX4351NE
MSL 1
4.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
4.3 Soldering Profile
Provided in the table below is the IPC/JEDEC J-STD-020 Classification Temperature (TC) and the maximum dwell
time the body temperature of these surface mount devices may be (TC - 5)°C or greater. The Classification
Temperature sets the Maximum Body Temperature allowed for these devices during reflow soldering processes.
Device
Classification Temperature (TC)
Dwell Time (tp)
Max Reflow Cycles
IX4351NE
260°C
30 seconds
3
4.4 Board Wash
IXYS Integrated Circuits recommends the use of no-clean flux formulations. Board washing to reduce or remove flux
residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to
the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up
bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the
variability of the wash parameters used to clean the board, determination of the bake temperature and duration
necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning
or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the
device must not be exposed to halide flux or solvents.
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13
IX4351NE
INTEGRATED CIRCUITS DIVISION
4.5 Mechanical Dimensions
4.5.1 IX4351NE 16-Pin Narrow SOIC Package
Recommended PCB Pattern
0.25 - 0.50 x 45º
(0.010 - 0.020 x 45º)
9.90 BSC
(0.390 BSC)
See Note 3
3.90 BSC
(0.154 BSC)
See Note 4
4.55
(0.179)
2.40
(0.094)
6.00 ± 0.50 BSC
(0.236 ± 0.020 BSC)
*
0.20 TYP
(0.008 TYP)
0.31 - 0.51
(0.012 - 0.020)
0.60
(0.024)
1.25 min
(0.049 min)
1.70
(0.059)
1.27 TYP
(0.05 TYP)
1.70 max
(0.067 max)
5.50
(0.217)
1.27
(0.05)
* Connect thermal pad to VSS or leave open.
0º - 8º
0.80 ± 0.50
(0.031 ± 0.020)
0.00 - 0.15
(0.000 - 0.006)
3.86 - 4.57
(0.152 - 0.180)
DIMENSIONS
mm
(inches)
NOTES:
1. All dimensions are MM (IN)
2. Reference JEDEC outline: MS-012 BC Rev F. (Thermal)
3. Dimension does not include mold flash, protrusions,
or gate burrs. Mold flash, protrusions, and gate burrs
shall not exceed 0.15 (0.006) per side.
4. Dimension does not include inter-lead flash, and
protrusions shall not exceed 0.25 (0.010) per side.
5. The thermal pad on the bottom of the device may be
connected to VSS or left floating; it must not be connected
to any other signal.
The thermal pad is not intended to carry current.
1.68 - 2.41
(0.066 - 0.095)
4.5.2 IX4351NETR Tape & Reel Packaging for 16-Pin Narrow SOIC Package
330.2 DIA.
(13.00 DIA.)
0.30 ± 0.05
(0.012 ± 0.002)
P1=8.00 ± 0.10
(0.315 ± 0.004)
2.00 ± 0.10 Note 3
(0.079 ± 0.004)
4.00 Note 1
(0.157)
∅ 1.5 +0.1 / -0.0
1.75 ± 0.10
(0.069 ± 0.004)
A
R 0.3 max
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
B0=10.30 ± 0.10
(0.406 ± 0.004)
K0=2.10 ± 0.1
(0.083 ± 0.004)
Embossed Carrier
Section A-A
Embossment
∅ 1.50 min A
7.5 ± 0.10 Note 3
R 0.5 typ
(0.295 ± 0.004)
16.0 ± 0.3
Direction of feed
(0.63 ± 0.012)
A0=6.50 ± 0.10
(0.256 ± 0.004)
NOTES:
1.10 Sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Dimensions
mm
(inches)
For additional information please visit our website at: https://www.ixysic.com
Disclaimer Notice - Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and
test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications.
Read complete Disclaimer Notice at https://www.littelfuse.com/disclaimer-electronics.
Specification: DS-IX4351NE-R03
©Copyright 2021, Littelfuse, Inc.
All rights reserved. Printed in USA.
4/30/2021
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