IXFC24N50Q

ADVANCE TECHNICAL INFORMATION VDSS HiPerFETTM MOSFETs ISOPLUS220TM Electrically Isolated Back Surface IXFC 26N50 IXFC 24N50 ID25 RDS(on) 500 V 23 A 500 V 21 A trr ≤ 250 ns 0.20 Ω 0.23 Ω N-Channel Enhancement Mode High dV/dt, Low trr, HDMOSTM Family ISOPLUS 220LVTM VDSS VDGR TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MΩ 500 500 VGS VGSM Continuous Transient ±20 ±30 ID25 TC = 25°C IDM TC = 25°C, Pulse width limited by TJM IAR TC = 25°C EAR TC = 25°C dv/dt IS ≤ IDM, di/dt ≤ 100 A/µs, VDD ≤ VDSS TJ ≤ 150°C, RG = 2 Ω PD TC = 25°C TL VISOL 50/60 Hz, RMS V V 30 mJ 5 V/ns 230 W -55 ... +150 150 -55 ... +150 °C °C °C 300 °C 2500 V~ 3 g O A A A A A A t = 1 minute leads-to-tab Symbol Test Conditions VDSS VGS = 0 V, ID = 250uA VGS(th) VDS = VGS, ID = 4mA IGSS VGS = ±20 VDC, VDS = 0 IDSS VDS = 0.8•VDSS VGS = 0 V RDS(on) VGS = 10 V, ID = IT Notes 1 & 2 © 2003 IXYS All rights reserved V V 23 21 92 84 26 24 1.6 mm (0.062 in.) from case for 10 s O Weight 26N50 24N50 26N50 24N50 26N50 24N50 BS TJ TJM Tstg Maximum Ratings E Test Conditions LE T Symbol Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 500 2 V 4 V ±100 nA TJ = 25°C TJ = 125°C 200 1 µA mA 26N50 24N50 0.20 0.23 Ω Ω G D S G = Gate S = Source Isolated back surface* D = Drain Features z Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation z Low drain to tab capacitance(