IXFR26N50

Advanced Technical Information HiPerFETTM Power MOSFETs IXFR 26N50 ISOPLUS247TM VDSS ID25 500 V 24 A 500 V 22 A trr £ 250 ns IXFR 24N50 (Electrically Isolated Back Surface) RDS(on) 0.20 W 0.23 W N-Channel Enhancement Mode High dV/dt, Low trr, HDMOSTM Family Symbol Test Conditions VDSS VDGR TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MW 500 500 V V VGS VGSM Continuous Transient ±20 ±30 V V ID25 TC = 25°C IDM TC = 25°C, Pulse width limited by TJM IAR TC = 25°C 26 24 104 96 26 24 A A A A A A EAR TC = 25°C 30 mJ dv/dt IS £ IDM, di/dt £ 100 A/ms, VDD £ VDSS TJ £ 150°C, RG = 2 W 5 V/ns PD Maximum Ratings 26N50 24N50 26N50 24N50 26N50 24N50 TJ TJM Tstg 1.6 mm (0.062 in.) from case for 10 s VISOL 50/60 Hz, RMS 250 W -55 ... +150 150 -55 ... +150 °C °C °C 300 °C 2500 V~ 6 g t = 1 minute leads-to-tab Weight Symbol Test Conditions VDSS VGS = 0 V, ID = 250uA VGS(th) VDS = VGS, ID = 4mA IGSS VGS = ±20 VDC, VDS = 0 IDSS VDS = 0.8 • VDSS VGS = 0 V RDS(on) VGS = 10 V, ID = IT Notes 1 & 2 Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 500 2 V 4 V ±100 nA TJ = 25°C TJ = 125°C 200 1 mA mA 26N50 24N50 0.20 0.23 W W IXYS reserves the right to change limits, test conditions, and dimensions. © 2000 IXYS All rights reserved G D Isolated back surface* G = Gate S = Source D = Drain * Patent pending Features TC = 25°C TL ISOPLUS 247TM • Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation • Low drain to tab capacitance(