LDS8161/41
6-Channel / 4-Channel High-Side Linear WLED Driver
with LED Temperature Compensation Using LED-SenseTM , I 2C, and Digital PWM
FEATURES
TM
Six (8161) / or Four (8141) Power-Lite Linear LDO
current regulators with 50 mV dropout in a highside driver topology.
High temperature LED current de-rating using the
TM
LED-Sense temperature compensation
algorithm, which directly monitors an LED PN
junction. No external temperature sensor is
required.
2
I C compatible serial programming interface
2
LED current programmable via I C from 0 to
~32 mA in 256 linear steps. Three (8161) or two
(8141) separately controlled driver banks with 2
LED drivers each
Integrated PWM generator for LED dimming with
12-bit resolution and 256 I2 C-programmable
logarithmic duty cycle steps from 0% to 100%
(~0.17 dB per step)
Total combined dimming range of > 16,384:1
Power efficiency up to 98%; average efficiency
> 80% in Li-ion battery applications
Low current shutdown mode ( < 1 µA );
Soft start and current limiting
LED Short circuit detection and protection, LED
open detection
Thermal shutdown protection
Low EMI.
Available in 3 mm x 3 mm x 0.8 mm 16-pin TQFN
package
APPLICATIONS
Keypad and Display Backlight
Cellular Phone
PDAs and Smartphones
DESCRIPTION
The LDS8161 is a 6-channel and the LDS8141 is a 4channel linear LED driver for WLED applications. It
includes ultra low dropout LDO current regulators at a
maximum 31.875 mA per channel in a common
cathode high side driver topology.
The LDS8161/LDS8141 has an average efficiency of
> 80% in Li-ion battery applications. It includes three
(LDS8161) or two (LDS8141) 8-bit current setting
DACs (one per bank) allowing LED currents to be
2
programmed via an I C-compatible serial interface
from 0 to 31.875 mA in 256 steps of 125A per step.
The LDO drivers have a low dropout voltage of
50 mV typically at maximum rated current. This
provides a low power/low EMI solution in Li-ion
battery applications without voltage boosting and
associated external capacitors and components.
High temperature current de-rating insures LED
reliability and provides automatic adjustment of LED
current to achieve maximum specified LED
brightness across the ambient temperature range.
TM
The
proprietary
LED-Sense
temperature
compensation algorithm directly monitors the junction
temperature of an LED and applies current de-rating
per a user loadable LUT (look up table) in 5ºC steps.
No external temperature sensing device is needed.
An integrated 12-bit PWM generator with “smooth”
logarithmic control supports LED dimming and high
temperature current de-rating. The PWM duty cycle is
2
programmable via the I C serial interface from 0% to
100%. User programmed 8-bit codes are converted
to 12-bit resolution logarithmic steps of ~ 0.17 dB per
step. The PWM frequency is ~280 Hz to minimize
noise generation.
The EN logic input functions as a chip enable. A logic
HIGH applied at the EN pin allows the
2
LDS8161/LDS8141
to
respond
to
IC
communications. An external serial interface address
pin is available for use in multi-target applications.
The device operates from 2.5V to 5.5V.
The LDS8160 is available in a 3 x 3 x 0.8 mm
16-lead TQFN package.
3
LDS8161/41
TYPICAL APPLICATION CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Parameter
V IN, LEDx
EN, SDAT, SCLK, SADD voltage
Storage Temperature Range
Junction Temperature Range
Soldering Temperature
HBM
ESD Protection Level
MM
© 2009 IXYS Corp.
Characteristics subject to change without notice
Rating
6
V IN + 0.7V
-65 to +160
-40 to +125
300
2
200
2
Unit
V
V
°C
°C
°C
kV
V
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
RECOMMENDED OPERATING CONDITIONS
Parameter
VIN
ILED per LED pin
Total Output Current ILOAD
Junction Temperature Range
Rating
2.5 to 5.5
0 – 31.875
191.25
-40 to +125
Unit
V
mA
mA
°C
Typical application circuit with external components is shown on page 1.
ELECTRICAL OPERATING CHARACTERISTICS
(Over recommended operating conditions unless specified otherwise) VIN = 3.6V, CIN = 1 µF, EN = High, TAMB = 25°C
Name
LEDx Channel Current DAC Range
# of LEDx Current steps (linear steps)
LEDx Current DAC Resolution/step
EN = VIN
6/4 Channels at 100%
Quiescent Current
DC PWMs and Temp
De-Rating Active
Shutdown Current
LED Current Accuracy
LED Channel Matching
Line Regulation
1
Load Regulation
2
Dropout Voltage
PWM Frequency
# of PWM duty cycle steps
Conditions
Min
0
2
Standby (no I C clock)
ILOAD = 120 mA/ 80 mA
ILOAD = 60 mA / 40 mA
VEN = 0V
5 mA ≤ILED ≤30 mA
(ILED - ILEDAVG ) / I LEDAVG
2.7 V ≤VIN ≤4.2 V
0.2 V < Vdx < 1.2 V
1 mA ≤ILED ≤30 mA
Log Mode steps
Minimum PWM On Time
PWM resolution
PWM Step Size
of
PWM Steps for current de-rating
Log Mode
Log Mode
1-x Scale Mode
2-x Scale Mode
De-rating Temperature Adjust Steps
Programmable De-rating Start
Temperature (Tj) Range (typical)
Programmable LED Shutdown
Temperature(Tj) Range (typical)
Input current
EN Pin
Logic Level
High
Low
Input Current Limit
Thermal Shutdown
Thermal Hysteresis
Wake-up/Shutdown Delay Time from EN
Raising/Falling Edge
3
Output short circuit Threshold
Note:
Active mode, EN = VIN
Normal Standby
Active Mode or Normal
Standby Mode
Soft ramp disabled
Soft ramp enabled
ILED = 20 mA
Typ
Max
31.875
256
0.125
125
0.6/0.45
0.45/0.35 0.35
0.5
1
±1.5
±1.5
2
1
50
75
285
256
13.7
12
0.17
-7
0
-14
0
5
Units
mA
steps
mA
µA
mA
mA
µA
%
%
%/V
%/V
mV
Hz
µs
bits
dB
PWM
0
Steps/5 C
0
C
30
55
80
0
80
105
120
0
-1
1
5
1.2
0.4
450
150
20
10
250
0.14
C
C
µA
V
mA
°C
ms
ms
V
1. Vdx = Vin – V F,
2. Vdx = Vin – V F, at which IILED decreases by 10% from set value
3. Minimum LED forward voltage, which will be interpreted as “LED SHORT” condition
© 2009 IXYS Corp.
Characteristics subject to change without notice
3
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
I 2C CHARACTERISTICS
Over recommended operating conditions unless otherwise specified for 2.7 VIN 5.5V, over full ambient temperature range -40 to +85ºC.
Symbol
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tBUF
tAA
tDH
Parameter
SCL Clock Frequency
Hold Time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up Time for a repeated START condition
Data In Hold Time
Data In Set-up Time
Rise Time of both SDAT and SCLK signals
Fall Time of both SDAT and SCLK signals
Set-up Time for STOP condition
Bus Free Time between a STOP and START condition
SCLK Low to SDAT Data Out and ACK Out
Data Out Hold Time
Min
0
0.6
1.3
0.6
0.6
0
100
Max
400
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
0.9
300
300
0.6
1.3
0.9
300
2
Figure 1: I C Bus Timing Diagram
READ OPERATION:
Option 1: Standard protocol sequential read:
S
Slave Address
R
A
Data 0
A
Data 1
A
From: Reg. m
Reg. m+1
where Reg. m is the last addressed in the write operation register
Data 2
Data n
A*
Reg. m+2
Reg. m+n,
P
Option 2: Random access:
S
Slave Address
R
A
Data m
A*
P
From reg. m, where Reg. m is the last addressed in the write operation register
Option 3: Random access with combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
R
A
Data m
A*
P
WRITE OPERATION:
Option 1: Standard protocol sequencial write:
S
Slave Address
W
A
Register Address m
A
Data 0
To: Reg. m
© 2009 IXYS Corp.
Characteristics subject to change without notice
4
A
Data 1
Reg. m+1
A
Data 2
Reg. m+2
Data k
A*
P
Reg. m+k
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Option 2: Combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
W
A
Data
A*
P
To: Reg. m
S: Start Condition
Sr Start Repeat Condition
R, W: Read bit (1), Write bit (0)
A: Acknowledge (SDAT high)
A*: Not Acknowledge (SDAT low)
P: Stop Condition
Slave Address: Device address 7 bits (MSB first).
Register Address: Device register address 8 bits
Data: Data to read or write 8 bits
- send by master
- send by slave
I2 C BUS PROTOCOL
Standard protocol
Combined protocol:
WRITE INSTRUCTION SEQUENCE
Standard protocol:
Write Instruction Example - Setting 20mA Current in LEDB1 and LEDB2
© 2009 IXYS Corp.
Characteristics subject to change without notice
5
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
LDS8161 / 41 REGISTERS DEFINITION AND PROGRAMMING
Note: Unlisted register addresses are for factory use only; For proper operation write only to registers defined.
ADDRESS
00h
01h
02h
DESCRIPTION
Bank A Current setting
Bank B Current setting
Bank C Current setting
(8161 only; Not for 8141)
BITS
8
8
8
Channel Enable
(No Bits 5, 4 for C2 and
C1 respectively for 8141)
6
Bank A, B, C PWM Duty
Cycle
8
19h
LED Diagnostics Test
8
1Ch
LED Faults Status
( shorted to GND)
5
1Dh
LED Faults Status
(shorted to VIN/open)
5
1Eh
1Fh
Configuration register
Software reset, Standby
8
8
49h
Ta-Tj Temperature Offset
8
4Ah
LED Shutdown
Temperature
5
4Bh
2-x Table enable and
breakpoint (T-code)
6
56h – 5Dh
Temp De-rating LUT
25C to 100C
(one 5C step every
nibble)
ΔPWM code1[7:4],
ΔPWM code0[3:0] –
ΔPWM code13[7:4],
ΔPWM code12[3:0]
8
03h
05h
© 2009 IXYS Corp.
Characteristics subject to change without notice
NOTES
Reg00h – Reg02h data code = (ILED / 0.125 mA) (decimal)
converted into hex format
Bits 5:0 = 1 enables LEDs C2, C1, B2, B1, A2, A1
respectively (See
Table 1). Both LEDs from one bank should be disabled to
minimize power consumption.
Log Mode:
~ – 0.17dB dimming per LSB for currents > 300 µA; Refer to
8 to 12 bit conversion curve (Figure 3 and Table 10) for
resolution in range 0 – 300 µA
Data Code 00h = 0% Duty Cycle, FFh = 100% Duty Cycle
Example: 50% brightness reduction ( – 6dB) requires: 255 –
(– 6 dB / – 0.17 dB) = 255 – 35 = 220 (decimal) = DCh steps
See Table 2; Bit 5 = 1 sets user-initiated LED short/open
diagnostic
Bits from bit 5 to bit 0 represent LED status for LEDC2 –
LEDA1 respectively. Bit = 1 represents LED shorted to GND
Bits from bit 5 to bit 0 represent LED status for LEDC2 –
LEDA1 respectively. Bit = 1 represents LED shorted to
VIN /open
See Table 3
See Table 4
Since junction temperature is measured, the values loaded
here allow an offset to account for Tj – Ta gradient.
This allows de-rate tables to be referenced to Ta levels.
Two 4 bit offsets value for the LED and the Si Diode;
Bit [7:4] = Tj-Ta offset for the LEDs
Bit [3:0] = Tj-Ta offset for the Si diode.
Typically should set both offsets to be equal.
See Table 5 & 6
Defines T-code, at which LED current shuts down per LED
vendor de-rating specification (see Table 5); Factory default
0
value = 11100 (bin) = 1Ch represents 105 C Tj
Bit 5 = 1 – enable 2-x scale LUT ΔPWM code correction (derating) starting at the breakpoint set by T-code (bits 4:0)
Bit 5 = 0 – 1-x scale (default) for entire temperature range
Bit [4:0] defines T-code, where temperature de-rating starts,
or where 2-x scaling begins (see Table 5)
2
Two LUT words per I C address.
Each word contains two 4-bit numbers repres enting of ΔPWM
codes. See
Table 6 and Appendix 1 for LUT programming.
Factory default setting is Logarithmic Mode table for WLED
LED (Nichia NSSW020BT WLED).
Default table could be used for WLED de-rating.
De-Rating starts at 55ºC junction.
6
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
A0h
Silicon diode dV F/dT [7:0]
8
A2h
LED dV F/dT [7:0]
8
Silicon diode η[7:0]
8
D4h
Silicon diode R s offset
[7:0]
8
D6h
LED Rs offset [7:0]
8
C0h
Silicon diode VF temperature coefficient (K factor) :
Factory recommended loaded value is 36h = -1.71 mV/°C =
001 10110 (bin),
where bits from bit 7 to bit 5 represent integer part
[1(decimal) = 001 (bin)], and bits from bit 4 to bit 0 – fractional
part [0.710 / 0.03125 = 22 (decimal) = 10110 (bin)]
User-loaded VF temperature coefficient @ 1mA for LEDs
used at Banks A, B, C respectively.
Negative tracking is assumed with temperature;
Bits from bit 7 to bit 5 represent integer part and
bits from bit 4 to bit 0 - fractional part of the coefficient
0
Example: Temperature coefficient = -2.26 mV/ C;
Bit 7 – bit 6 = 2 (decimal) = 010 (bin), and
Bit 4 – bit 0 = INT{0.26 / 0.03125} = 8 (decimal) = 01000 (bin)
User loads 010 01000 (bin) = 48h = -2.25 (closest setting)
Silicon diode η(eta, or non-ideality factor):
Factory recommended loaded value is default is 1.00 =
01000000(bin) = 40h
Bits from bit 7 to bit 5 represent integer part and
bits from bit 4 to bit 0 - fractional part (resolution = 0.015625
per LSB)
Example: η= 1.00;
Bit 7 – bit 6 = 1 (decimal) = 01 (bin), and
Bit 5 – bit 0 = INT{0.00 / 0.015625} = 0 (dec) = 000000 (bin)
User loads 01 000000 = 40h = 1.00
Silicon diode series resistance offset
Factory recommended loaded value = 04h = ~ 68 ohms
-6
Formula (decimal) = 8192 x [(68 ohms x 8 x 10 A)/1.14 V]
LED Rs offset (user-loaded) for Banks A, B, and C LEDs
Typically LED Rs = 5 – 30 Ω
User loads per LED used. (1/slope of high current region of
LED I-V characteristic).
-4
Formula (decimal) = 8192 x [(Rs Ωx 8 x 10 A) / 1.14V]
Table 1
Register
Address
03h
(8161)
(8141)
Bit 7
LED
OT
Flag
Same
Channel Enable Register
Bit 4
Bit 3
Bit 2
Bit 6
Bit 5
N/A
Enable C2
Enable C1
Enable B2
N/A
N/A
N/A
Same
Bit 1
Bit 0
Enable B1
Enable A2
Enable A1
Same
Same
Same
Table 2
Register
Address
19h
Bit 7
Factory
Only
0*
Bit 6
Factory
Only
0*
Bit 5
Diagnostics
Request
0*
Digital Test Modes Register
Bit 4
Bit 3
Bit 2
Slow Ramp Fast PWM
Factory
Bypass = 1
adjust =1
Only
0*
Normal = 0*
0*
Bit 1
Post ADC Filter
Enable =1
Filter Off=0*
Bit 0
Factory
Only
0*
Note: *) Value by default
© 2009 IXYS Corp.
Characteristics subject to change without notice
7
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Table 3
Register
Address
1Eh
Bit 7
Factory Set
1*
Factory trimmed;
User should write 0
Configuration Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Factory Factory Factory Factory
dT adjust
Only
Only
Only
Only
disabled = 1*
dT adjust
0*
0*
0*
0*
enabled = 0
Bit 1
Soft Start
disabled = 1
Soft Start
enabled = 0*
Bit 0
Factory
Only
0*
Note: *) Value by default
Table 4
Register
Address
1Fh
Note:
Bit 7
Software
reset = 1
Bit 6
Standby
mode = 1
Bit 5
Temperature
request = 1
Control Register
Bit 4
Calibration
request = 1
Normal operation = 0*
Bit 3
Custom OSC
trim = 1
Factory
preset = 0*
Bit 2
Bit 1
Bit 0
Osc
trim 2
**
Osc
trim 1
**
Osc
trim 0
**
*) Value by default
**) Trim code defined by customer
Bit 7 = 1 — Software reset: resets device, all registers reset/cleared.
Bit 6 = 1 — Standby (oscillator disabled, all registers retain programmed values.)
Table 5: Ta-Tj Temperature Gradient Offset
( Set offset code to match reference De-rate point in LUT from LED Tj to Ta. Typically LED and Si are equal)
Register
Address
49h
Note:
Bit 7
LED
Offset 3
0*
Bit 6
LED
Offset 2
0*
Bit 5
LED
Offset 1
0*
Control Register
Bit 4
Bit 3
LED
Si Diode
Offset 0
Offset 3
0*
0*
Bit 2
Si Diode
Offset 2
0*
Bit 1
Si Diode
Offset 1
0*
Bit 0
Si Diode
Offset 0
0*
*) Value by default
Table 6: Offset Codes for Tj-Ta Temperature Gradient Offset (both LED and Si per Table 5).
Temperature
0
Offset C
(Ta-Tj)
-40
-35
-30
-25
Bit3– Bit
0
1000
1001
1010
1011
Temperature
0
Offset C
(Ta-Tj)
-20
-15
-10
-5
Bit3– Bit
0
1100
1101
1110
1111
Temperature
0
Offset C
(Ta-Tj)
0
5
10
15
0000
0001
0010
0011
Temperature
0
Offset C
(Ta-Tj)
20
25
30
35
Bit4 –
Bit 0
10110
10111
11000
11001
11010
Temperature
0
C
100
105
110
115
120
Bit3–
Bit 0
Bit3–
Bit 0
0100
0101
0110
0111
Table 7: T-code values vs. Temperature (for registers 4Ah & 4Bh)
Temperature
0
C
25
30
35
40
45
Bit4 –
Bit 0
01100
01101
01110
01111
10000
Temperature
0
C
50
55
60
65
70
© 2009 IXYS Corp.
Characteristics subject to change without notice
Bit4 –
Bit 0
10001
10010
10011
10100
10101
Temperature
0
C
75
80
85
90
95
8
Bit4 –
Bit 0
11011
11100
11101
11110
11111
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Table 8: LDS8161 / 41 Temperature De-rating LUT Register Allocation
(data stored is PWM code per each temperature point)
Data bits
Register
Address
Data bits
7 –4
3– 0
ΔPWM code for
0
temperature, C
Register
Address
7–4
3–0
ΔPWM code for
0
temperature, C
56h
30
25
5Ah
70
65
57h
58h
59h
40
50
60
35
45
55
5Bh
5Ch
5Dh
80
90
100
75
85
95
Table 9: Valid ΔPWM Codes vs. Number of Adjustment Steps for LDS8161/ 41 De-rating
Number of
steps
Not Used
-7
-6
-5
Binary
Code
1000
1001
1010
1011
Number of
steps
-4
-3
-2
-1
Binary
Code
1100
1101
1110
1111
Number of
steps
0
Not Used
Not Used
Not Used
Binary
Code
0000
0001
0010
0011
Number of
steps
Not Used
Not Used
Not Used
Not Used
Binary
Code
0100
0101
0110
0111
PROGRAMMING EXAMPLES
Operation
Set 20 mA current at Bank LEDA
Set 30 mA at LEDA, 30 mA at LEDB, & 20 mA at LEDC banks
Turn LEDs A1, B1 and C1 on, all others off
Turn LEDs A2, B2, and C2 on, all others off
Turn all LEDs on
Set Bank A,B,C PWM duty Cycle at 50% (-6 dB)
Disable Temperature De-rating (DT_Adjust_disable)
Re-Enable Temperature De-rating
Short/open LED diagnostic request
Read out LED short to GND status
Read out LED short to VIN /open status
Set Standby Mode
Resume normal operation from standby mode
Calibration request (conduct temperature calibration)
0
Set LEDs in shutdown mode at junction temperature above 100 C
Set Ta-Tj offset for LED and Si Diode to -20ºC
Software Reset (to default values) and/or clear of all registers
Note:
Register
Address
00h
00h
03h
03h
03h
05h
1Eh
1Eh
19h
1Ch
1Dh
1Fh
1Fh
1Fh
4Ah
49h
1Fh
Register Data
A0h
F0h F0h A0h
15h
24h
3Fh
DCh
04h
00h
20h
40h
00h
10h
1Bh
CCh
80h
Command
(hex)
XX 00 A0
XX F0 F0 A0
XX 03 15
XX 03 24
XX 03 3F
XX 05 DC
XX 1E 04
XX 1E 00
XX 19 20
XX 1C YY
XX 1D YY
XX 1F 40
XX 1F 00
XX 1F 10
XX 4A 1B
XX 49 CC
XX 1F 80
XX – The LDS8160 I2C customer-selected slave address followed by binary 1 for write command, i.e. if I2C slave address is
001 0001 (see Table 8), XX = 0010 0011 (bin) = 23h
YY – The LDS8160 I2C customer-selected slave address followed by binary 0 for read command, i.e. if I2C slave address is
001 0001 (see Table 8), YY = 0010 0010 (bin) = 22h
© 2009 IXYS Corp.
Characteristics subject to change without notice
9
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
PIN DESCRIPTION
Function
2
I C Serial clock input
2
I C Serial data input/output
2
I C Serial interface Address Programming
Ground Reference
Device enable (active high)
LEDC2 anode terminal -8161 (NC for 8141)
LEDC1 anode terminal -8161 (NC for 8141)
LEDB2 anode terminal
LEDB1 anode terminal
LEDA2 anode terminal
LEDA1 anode terminal
Power Source Input; connect to battery or supply
Test pin
Pin
Name
SCLK
SDAT
SADD
GND
EN
LEDC2
LEDC1
LEDB2
LEDB1
LEDA2
LEDA1
V IN
TST
Not connect (no internal connect to the device)
Connect to GND on the PCB
NC
PAD
Pin #
8161
8141
1
1
2
2
3
3
4
4
6
6
8
9
10
10
11
11
12
12
13
13
14
14
15
15
5, 7, 8,
5, 7, 16
9, 16
PAD
PAD
PIN FUNCTION
VIN is the supply pin. A small 1μF ceramic bypass
capacitor is required between the VIN pin and ground
near the device. The operating input voltage range is
from 2.5 V to 5.5 V.
GND is the ground reference for internal circuitry.
The pin must be connected to the ground plane on
the PCB.
LEDA1 – LEDC2 provide the internal regulated
current source for each of the LED anodes. These
pins enter high-impedance zero current state
whenever the device is in shutdown mode. LEDC1
and LEDC2 are no connects (NC) for the LDS8141.
EN is the enable input for the entire device.
Guaranteed levels of logic high and logic low are set
at 1.3 V and 0.4V respectively. When EN is initially
taken high, the device becomes enabled and may
2
communicate through I C interface
PAD is the exposed pad underneath the package.
For best thermal performance, the tab should be
soldered to the PCB and connected to the ground
plane
2
SDAT is the I C serial data line. This is a bidirectional
line allowing data to be written into and read from the
four registers in the driver..
TST is a test pin used by factory only. Leave it
floating (no external connection)
2
SCLK is the I C serial clock input.
2
SADD is I C Serial interface Addresses tie to either
GND or VIN pin to allow choice of two salve
addresses
© 2009 IXYS Corp.
Characteristics subject to change without notice
10
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
BLOCK DIAGRAM
VIN
All Drivers 0 to 31.875 mA
OverTemp
I2C Interface
Top Level Control
diagnostics
Shorted LED
Open LED
LED Calibration
Soft Start control
SCL
Vin to
al l
Drivers
PWM
Calibrated
Reference
Currents
and
ADC bias
currents
Bandgap
Voltage
Reference
1.2V
SDA
LEDA1
PWM
1.2V
32
ADC
10 bit SAR
10
Digital Temperature
Sensor / Abritrator
LEDA2
Pre-Scale
8x, 1x, or 1/4x
PWM
Si Iforce
LED Iforce
LEDB1
SAD
1 0 uA
2 uA 1 mA
0.2 mA
Temp
De-Rating
LUT
PWM
PWM
OTP
LEDB2
Si PNP
temp diode
Temp
Trim
PWM
Temp
De-Rating
Table
Temp to PWM
adjust LUTs
PWM
8 bit to 12 bit (log) PWM
Generator
LEDC1
(8161)
to PWM
PWM
OTP
Driver
1.8V
Gnd
GND
To top control
LEDC2
(8161)
to top control & dig processing
Vin
Vin to 1.8V LDO
for digital core
1.2V
POR
Start Up
Vin
Oscillator & Clock Generator
~ 1.2 MHz
EN
Figure 2: LDS8161/41 Functional Block Diagram
An initialization sequence then begins, taking less
than 10 ms. This sequence determines the user2
selected I C slave address, loads factory
programmed settings, and conducts diagnostics for
open/shorted LEDs.
BASIC OPERATION
The LDS8161 / 41 may operate in following modes:
a) Normal Operation Mode
b) Normal Standby Mode
c) Programming Modes
d) Shutdown Mode
2
At this point, the I C interface is ready for
communication and the LDS8161/41 may be userprogrammed. Upon programming completion for all
required initial parameters and features’ settings, a
calibration command is given by setting bit 4 of the
Control Register (1Fh) HIGH. This starts the
calibration sequence of the LDS8161/41 LEDTM
Sense temperature de-rating circuits and occurs
simultaneous with a gradual ramp-up of LED PWM
and current levels to the user programmed values.
This initialization is completed in less than 250 ms in
NORMAL OPERATION MODE
At power-up, V IN should be in the range from 2.5 V to
5.5 V (max). If V IN is slow rising, EN pin should be
logic LOW at least until VIN reaches a 2.5 V level.
When EN is taken HIGH, a soft-start power-up
sequence begins and performs an internal circuits
reset that requires less than 100 µs.
© 2009 IXYS Corp.
Characteristics subject to change without notice
11
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
the default soft-start ramp mode, or s less than 10 ms
with the soft-start ramp mode disabled by setting bit 1
of the Configuration Register (1Eh) HIGH.
e) Soft start-up PWM ramp feature enabled;
If the factory default loaded de-rating curve is used
as shown in Figure 7, then following Table 10
identifies the necessary registers and initialization
required after the power-up or reset state to operate
the LDS8161/41.
The calibration parameters for the temperature derating and all customer-set parameters remain intact
until the part is reset or powered-down. Additionally,
the user can re-calibrate LDS8161/41 during times
when LED currents are brought to zero and thermally
stabilized by programming the calibration command
bit as discussed.
Factory preset values (upon completion of the powerup initialization) are as follow (see Table 3):
a) All LEDs are disabled and ILEDA, B, C = 0;
b) WLED mode (i.e. 1 De-rating LUT) selected
and 1 PWM generator drives all 3 banks
(8160) or 2 banks (8141).
c) PWM dimming control is enabled Logarithmic
Mode with reset duty cycle = 0%.
TM
Figure 3: LDS8161/41 Default De-rate Curve
d) LED-Sense
temperature de-rating is
disabled with the LUT in Logarithmic Mode
for a Nichia NSSW020BT WLED;
Table 10: Recommended Register Load Sequence for LDS8161/41
(Using the Factory Default De-Rating LUT)
Reg Load
Sequence #
Reg
(hex)
Value (hex)
1
2
3
4
5
1Eh
49h
4Ah
4Bh
A0h
00h
CCh
18h
20h
36h
6
A2h
User Loads Per LED Used
7
8
C0h
D4h
40h
04h
9
D6h
User Loads Per LED Used
10
11
12
13
1Fh
00h
01h
02h
14
03h
15
05h
10h
User Loads Ex: F0h = 30mA
Uer Loads Ex: F0h = 30mA
User Loads Ex: F0h = 30mA
User Loads Ex: 3Fh = all
channels
User Loads Ex: FEh = 91% DC
© 2009 IXYS Corp.
Characteristics subject to change without notice
Comments
12
Initialize Configuration Register
Ta-Tj 0ffset = -20ºC
Set LED Shutdown Temp = 85ºC (Ta referenced)
Set 2x de-rate mode starting at 55C
Load Si Diode K factor for - 1.71mV/C
User loads LED K factor @ 1mA IF
29h = -1.3mV/C for Nichia NSSW020BT
Load Si Diode
ηfactor = 1.0
Load Si Diode Rs = 68 ohms
User loads LED Rs
61h = 17 ohms for Nichia NSSW020BT
User issues temp calibration command
User sets Current for Bank A.
User sets Current for Bank A.
User sets Current for Bank B.
User enabled LED channels
User sets PWM duty cycle for all channels
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
To turn LEDs ON/OFF register 03h should be
addressed with data that represents the desired
combination of LEDs turned ON/OFF (see Table 1);
i.e. if LEDC1, LEDC2, LEDA1, LEDA2 should be ON,
and LEDB1, LEDB2 should be OFF, binary code that
should be written into register 03h is 110011 (bin) =
33h.
The de-rate table stored in the correction LUT is
referenced to the LED Tj. Register 49h can be used
to apply the Ta-Tj temperature offset between the
ambient and LED junction temperature. This can
effect a +/- shift of the de-rating curve in the
Temperature axis to reference the de-rating profile to
ambient, and/or set the start of de-rating to the
desired ambient temperature level to accommodate
different LEDs and current/power levels. The default
table will de-rate the current ~ - 9.2 dB (0.348x) from
its user set low temperature maximum level over
35ºC (from the start of the de-rate temperature). For
example, if the LED current is set to 30mA prior to
de-rating, and de-rating begins at 55ºC, at 85ºC the
current is de-rated to 0.348 x 30mA = 10.4mA.
The LDS8161/41 allows two ways for LED current
setting and dimming; analog (static) dimming using
the 8 bit current DACs, and dynamic dimming via the
integrated 12-bit digital PWM. Combining both
methods allows for total dimming capability of >
16,384:1
Analog dimming using the current setting DACs
discussed via registers 00h – 02h is referred to as the
static mode. Digital dimming using the internal PWM
generator changes the duty cycle per the value set in
register 05h and therefore adjusts the average LED
current. This is referred to as dynamic mode.
Register 4Ah sets the LEDs shutdown junction
temperature per the T-codes provided in Table 7.
When this temperature is exceeded, all of the LED
current driver channels are disabled to insure no
damage to the LEDS. Additionally, an LED OT (over
temperature) status flag is set HIGH in Bit 7 of the
enable channel register 03h. If the flag is set the user
can re-enable the channels by re-writing to the
channel enable bits in register 03h, however the OT
flag will still remain HIGH, until the device is power
sequenced, reset, or placed in the shutdown mode.
For dynamic mode, the LDS8161/41 integrates a
digital PWM generator that operates at a frequency of
~ 285 Hz. It operates in Logarithmic Mode. The PWM
generator has 12-bit resolution and can be
programmed with an 8-bit code to provide 256
internally mapped 12-bit logarithmic duty cycle steps
to adjust the dimming level
The advantage of PWM dimming is stable LED color
temperature / wavelength that is determined by the
maximum static mode LED current value set by
registers 00h – 02h. The integrated PWM generator
reduces the system requirement to provide a
continuous pulsed waveform.
If a Ta-Tj offset is used other than 00h (i.e. 0ºC) in
register, 49h, than the shutdown junction temperature
loaded in 4Ah should also include this offset. This
insures the LED shutdown is also properly referenced
to ambient level, Ta.
To use the dynamic PWM mode for LED current
setting, the maximum ILED value should first be set by
current DAC registers 00h – 02h as described above
for static mode, and desired dimming / duty cycle can
be set by register 05h. The logarithmic operating
mode provides a dimming resolution of approximately
-0.17 dB per step with 0dB dimming (i.e. 100% duty
th
cycle) at the 256 step (i.e. FFh), and 0% duty cycle
(~ -80 dB dimming) at 00h.
LED Current Setting
Current setting registers 00h – 02h should be
2
programmed using I C interface and desired LEDs
should be enabled using register 03h before LEDs
turn on.
2
The standard I C interface procedure is used to
2
program ILED current (see chapter “I C INTERFACE”).
LDS8161/41 should be addressed with slave address
chosen (see Table 11 for accessible slave
addresses) followed by register address (00h, 01h, or
02h) and data that represents the code for the
desired LED current.
LED-Sense
High Temperature Current De-rating
TM
The LDS8161/41 integrates the IXYS LED-Sense
temperature measurement and high temperature
current de-rating algorithm to insure LED reliability
and operating lifetimes.
Code for LED current is determined as ILED/0.125 mA
in hex format, i.e. 20 mA current code = 20/0.125 =
160 (dec) = A0h.
LED current is de-rated via reductions in PWM duty
cycle to meet LED vendor power dissipation vs. LED
junction temperature specifications.
The maximum current setting is 31.875 mA. Since
the LDS8161/41 is a low drop-out LDO based linear
LED driver, when using maximum current levels,
users should
select LEDs with V F < 3.3V to
maximize operation with Li-ion batteries.
© 2009 IXYS Corp.
Characteristics subject to change without notice
TM
User programmable de-rating adjustments are stored
in a correction LUT comprised of eight 8-bit registers
from 56h to 5Dh. Each register stores a 4-bit
13
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
adjustment code for two 5ºC temperature steps in its
lower (bits 3:0) and higher (bits 7:4) nibble. User
loadable de-rating codes in the 1x scale mode
represent 0 to -7 PWM de-rating steps. In the 2 x
scale mode the de-rating codes represent 0 to -14
PWM steps.
adjust the PWM duty cycle. Therefore this reduces
the av erage current through the LEDs as defined by
the LUT table.
The user loads specific ΔPWM de-rating codes into
the LUT (56h – 5Dh) for every 5ºC temperature step
from 25ºC to 100ºC to meet desired current and
power vs. LED junction temperature.
LUT de-rating correction codes are subtracted from
the user-set duty cycle/dimming code (dynamic
mode) loaded in register 05h to maintain reliable LED
current levels.
The LDS8161/41 includes a 10-bit ADC and digital
processing engine to determine LED temperatures
approximately every 2.5 seconds. The proprietary
TM
LED-Sense algorithm allows direct measurement of
LED junction temperatures on the LEDA1 driver
channel, without the need for an external temperature
sensor. Additionally an on-chip silicon temperature
sensing diode is also measured to enhance
temperature estimation accuracy.
Figure 4: Dynamic Mode Dimming in Logarithmic
Mode in dB vs. register 05h data
(0dB dimming = full LED brightness)
Additionally, the ADC and processing circuits are
time-multiplexed to provide an LED opens and shorts
diagnostic feature.
A Factory loaded de-rating curve is valid upon reset,
and provide the de-rating profile shown at Figure 3.
2
I C Interface
2
The LDS8160 uses a 2-wire serial I C-bus interface.
2
The SDAT and SCLK lines comply with the I C
electrical specification and should be terminated with
pull-up resistors to the logic voltage supply. When the
bus is not used, both lines are high. The device
supports a maximum bus speed of 400kbit/s. The
serial bit sequence is shown at REGISTER
DEFINITION AND PROGRAMMING section for read
and write operations into the registers. Read and
write instructions are initiated by the master
controller/CPU and acknowledged by the slave LED
driver.
Figure 5: Dynamic Mode Dimming in Logarithmic
Mode in percent vs. register 05h data
(0% dimming = full LED brightness)
The LDS8161/41 allows user to choose between two
2
I C addresses by connecting SADD pin (#3) either to
ground, or VIN pin (see Table ).
Additionally, the LED drivers are disabled (i.e. 0 DC
current) if the measured LED junction temperature
exceeds a preset value that is loaded in register 4Ah.
The default is set for 1Ch = 105ºC Tj.
2
Table 11: LDS8161/41 I C Slave Addresses
SADD pin
connected to
Ground
V IN
TM
The LED-Sense engine periodically measures the
LED junction temperature on channel LEDA1 and
encodes the value into 5-bit T-codes representing
0
0
5 C temperature intervals from -35 to +120 C.
Hex
11h
55h
2
For further details on the I C protocol, please refer to
2
the I C-Bus Specification, document number 9398393-40011, from Philips Semiconductors.
The measured T-code value addresses the stored
ΔPWM de-rating codes stored in the LUT registers to
© 2009 IXYS Corp.
Characteristics subject to change without notice
2
I C Address
Binary code
001 0001
101 0101
14
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Unused LED Channels
level to shutdown VIN power to prevent possible
damage to the LED. The combined series resistance
of the LED (typically ~ 10Ω or more) and additional
board series resistance will result in current limiting
but not sufficient to insure no damage to low power
LEDs.
For applications with less than six (8161) or four
(8141) LEDs, the unused LED channels can be
2
disabled via the I C interface by addressing register
03h with data that represents the desired
combination of LEDs turned ON/OFF (see Table 1).
Besides the power-up diagnostic sequence, the user
can re-initiate a diagnostic command at any time by
setting bit 5 of the Digital Test Modes Register, 19h,
to HIGH.
The LDS8161/41 unused LED outputs can be left
open.
Parallel-Connected LED Channels for Higher
Current LEDs
The LDS8161/41 restores LED current to
programmed value at channels with detected shorts
to GND after the fault condition is removed.
In higher power LED applications requiring more than
31.875 mA DC current, LED driver channels can be
connected in parallel.
Over-Temperature Protection
For example, ½ watt, 150 mA LEDs can be driven
with the LDS8161 by paralleling all 6 channels with
25 mA per channel. Likewise, the LDS8141 can drive
up to 127.5 mA by connecting all 4 channels in
parallel at the maximum 31.875 mA per channel.
If the die temperature exceeds +150°C, the driver will
enter shutdown mode. The LDS8161/41 requires
restart after die temperature falls below 130°C.
LED Selection
LED short/open protection
If the power source is a Li-ion battery, LEDs with V F =
1.9 V - 3.3 V are recommended to achieve highest
efficiency performance and extended operation on a
single battery charge.
The LDS8161/41 runs a LED short/open diagnostic
routine upon the power up sequence. It detects both
LED pins shorted to ground and LED pins that are
open or shorted to V IN (fault conditions).
The results for short to GND detection are stored in
Diagnostics Register 1Ch. Bits from bit 5 to bit 0
indicate a short status as bit = 1 for LEDC2 - LEDA1
respectively. A short to GND is detected, if the
measured LED pin voltage is less than ~ 0.14 V
independent of the programmed LED current. Every
channel, detected as shorted, is disabled
External Components
The driver requires one external 1 µF ceramic capacitors (C IN) X5R or X7R type.
CONFIGURATION MODES
The LDS8161/41 allows the option to choose special
operating modes overwriting content of Configuration
Register 1Eh (see Table 2).
Test results for open or short to VIN LED pins are
stored in Diagnostics Register 1Dh, Bits from bit 5 to
bit 0 represent LEDC2 - LEDA1 respectively with bit
= 1 indicates fault condition at this particular LED pin.
Bit 1 allows bypass soft start / ramp down if fast
raising/falling LED current required.
Bit 2 allows disable LED temperature compensation if
desired.
An open LED pin fault causes no harm in the
LDS8161/41 or the LED as the high side driver has
no current path from V IN or GND. Therefore, the fault
detection status indicates only in the 1Dh diagnostic
register, and no further action is required.
The LDS8161/41 also provides the option for using
an external remote temperature-sensing diode device
such as a 2N3904. To use this option the diode
anode should be connected to channel LEDA1. The
cathode connected to GND. In this case, channel
LEDA1 should be disabled via register 03h and it
cannot operate as an LED current source.
In the case of an LED directly shorted to VIN , the full
V IN voltage will be connected to the LED and current
can flow independent of the LDS8161/41 LED driver
circuit directly to GND. The LDS8161/41 will detect
the fault and indicate the status in Register 1Dh,
however further action needs taken at the system
© 2009 IXYS Corp.
Characteristics subject to change without notice
Bits 0, 3, 4, 5, 6, and 7 of the Configuration Register
1Eh are for factory use only and should be set to 0 or
the user should use the power-on-reset values.
15
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
The LDS8161/41 wakes up from shutdown mode with
factory-preset default data. To preserve customerprogrammed data, use Normal standby mode.
STANDBY MODES
The LDS8161/41 has a “soft” standby or sleep mode,
2
which the customer may set by I C interface
addressing register 1Fh with bit 6 = 1 (see Table 4).
PROGRAMMING MODES
The LDS8161/41 is factory preprogrammed with a
default temperature de-rating LUT that works with the
Nichia NSSW020BT WLEDs or equivalent. However,
specific LEDs and other user system conditions may
require user programming of the temperature
compensation LUTs and other LED specific
parameters.
2
In the Standby Mode, the I C interface remains active
and all registers retain their programmed information.
In Standby Mode the LED drivers and internal clock
are powered off; however, internal regulators and
reference circuits remain active to insure power to the
digital sections to hold register values and maintain
2
I C interface communications. This results in standby
current ~ 125 µA typical. For this mode, the EN pin
should be logic HIGH with signal level from 1.3 to VIN
voltage.
After initialization and user programming the user
2
should conduct an I C calibration sequence
command by writing Bit 4 = 1 in the Control register
1Fh. This conducts a real time calibration of the initial
starting temperature and actual LED parameters.
Upon completion, Bit 4 will be internally reset to 0,
and the LDS8161/41 is ready for use.
SHUTDOWN MODE
To set LDS8161/41 into the shutdown mode, the EN
pin should be logic low more than 10 ms. The
LDS8161/41 shutdown current is less than 1 µA.
© 2009 IXYS Corp.
Characteristics subject to change without notice
16
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
PACKAGE DRAWING AND DIMENSIONS
16-PIN TQFN (HV3), 3mm x 3mm, 0.5mm PITCH
SYMBOL
A
A1
A2
b
D
D1
E
E1
e
L
m
n
MIN
0.70
0.00
0.178
0.20
2.95
1.65
2.95
1.65
0.325
NOM
0.75
0.02
0.203
0.25
3.00
1.70
3.00
1.70
0.50 typ
0.375
0.150 typ
0.225 typ
MAX
0.80
0.05
0.228
0.30
3.05
1.75
3.05
1.75
0.425
Note:
1. All dimensions are in millimeters
2. Complies with JEDEC Standard MO-220
© 2009 IXYS Corp.
Characteristics subject to change without notice
17
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
ORDERING INFORMATION
Part Number
LDS8161 002-T2
LDS8141 002-T2
Notes:
1.
2.
Package
Package Marking
TQFN-16 3 x 3mm
(1)
8161
TQFN-16 3 x 3mm
(1)
8141
Matte-Tin Plated Finish (RoHS-compliant)
Quantity per reel is 2000
EXAMPLE OF ORDERING INFORMATION
Prefix
LDS
Device #
Suffix
8161 or 8141
002
Product Number
Optional
Company ID
Package
T2
Tape & Reel
T: Tape & Reel
2: 2000/Reel
002: 3x3 TQFN
Notes:
1) All packages are RoHS-compliant (Lead-free, Halogen-free).
2) The standard lead finish is Matte-Tin.
3) The device used in the above example is a LDS8161A 002–T2 (3x3 TQFN, Tape & Reel).
4) For additional package and temperature options, please contact your nearest IXYS Corp. Sales office.
© 2009 IXYS Corp.
Characteristics subject to change without notice
18
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Appendix 1
# of steps
Hex code
Dimming,
dB
Dimming,
%
# of steps
Hex code
Dimming,
dB
Dimming,
%
# of steps
Hex code
Dimming,
dB
Dimming,
%
Table 5 Dynamic Mode Dimming in Logarithmic Mode vs. register 05h data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
-72.3
-66.3
-62.8
-60.3
-58.3
-56.7
-55.4
-54.3
-53.2
-52.3
-51.5
-50.7
-50
-49.4
-48.8
-48.2
-47.7
-47.2
-46.7
-46.3
-45.9
-45.5
-45.1
-44.7
-44.4
-44
-43.7
-43.4
-43.1
-42.8
-42.5
100
99.98
99.95
99.93
99.90
99.88
99.85
99.83
99.80
99.78
99.76
99.73
99.71
99.68
99.66
99.63
99.61
99.58
99.56
99.54
99.51
99.49
99.46
99.44
99.41
99.39
99.37
99.34
99.32
99.29
99.27
99.24
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
-41.9
-41.4
-40.9
-40.5
-40.1
-39.6
-39.2
-38.9
-38.5
-38.2
-37.8
-37.5
-37.2
-36.9
-36.6
-36.3
-36.1
-35.8
-35.5
-35.3
-35
-34.8
-34.6
-34.4
-34.1
-33.9
-33.7
-33.5
-33.3
-33.1
-32.9
-32.8
99.19
99.15
99.10
99.05
99.00
98.95
98.90
98.85
98.80
98.75
98.71
98.66
98.61
98.56
98.51
98.46
98.41
98.36
98.32
98.27
98.22
98.17
98.12
98.07
98.02
97.97
97.92
97.88
97.83
97.78
97.73
97.68
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
-32.6
-32.4
-32.2
-32.1
-31.9
-31.7
-31.6
-31.4
-31.3
-31.1
-30.9
-30.8
-30.7
-30.5
-30.4
-30.2
-30.1
-30
-29.8
-29.7
-29.6
-29.5
-29.3
-29.2
-29.1
-29
-28.8
-28.7
-28.6
-28.5
-28.4
-28.3
97.63
97.58
97.53
97.49
97.44
97.39
97.34
97.29
97.24
97.19
97.14
97.09
97.05
97.00
96.95
96.90
96.85
96.80
96.75
96.70
96.66
96.61
96.56
96.51
96.46
96.41
96.36
96.31
96.26
96.22
96.17
96.12
Continued
© 2009 IXYS Corp.
Characteristics subject to change without notice
19
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Table 10 Dynamic Mode Dimming in Logarithmic Mode vs. register 05h data
# of steps
Hex code
Dimming,
dB
Dimming,
%
# of steps
Hex code
Dimming,
dB
Dimming,
%
# of steps
Hex code
Dimming,
dB
Dimming,
%
Continue
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
-28.1
-27.9
-27.7
-27.5
-27.3
-27.1
-26.9
-26.7
-26.5
-26.3
-26.2
-26
-25.8
-25.7
-25.5
-25.3
-25.2
-25
-24.9
-24.7
-24.6
-24.5
-24.3
-24.2
-24
-23.9
-23.8
-23.7
-23.5
-23.4
-23.3
-23.2
96.02
95.92
95.83
95.73
95.63
95.53
95.43
95.34
95.24
95.14
95.04
94.95
94.85
94.75
94.65
94.56
94.46
94.36
94.26
94.17
94.07
93.97
93.87
93.77
93.68
93.58
93.48
93.38
93.29
93.19
93.09
92.99
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
-22.9
-22.7
-22.5
-22.2
-22
-21.8
-21.6
-21.4
-21.2
-21
-20.8
-20.6
-20.5
-20.3
-20.1
-20
-19.8
-19.6
-19.5
-19.3
-19.2
-19
-18.9
-18.7
-18.6
-18.4
-18.3
-18.1
-18
-17.9
-17.7
-17.6
92.80
92.60
92.41
92.21
92.02
91.82
91.63
91.43
91.24
91.04
90.84
90.65
90.45
90.26
90.06
89.87
89.67
89.48
89.28
89.09
88.89
88.70
88.50
88.31
88.11
87.92
87.72
87.52
87.33
87.13
86.94
86.74
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
-17.4
-17.1
-16.9
-16.6
-16.4
-16.2
-16
-15.8
-15.6
-15.4
-15.2
-15
-14.8
-14.6
-14.4
-14.3
-14.1
-13.9
-13.8
-13.6
-13.4
-13.3
-13.1
-13
-12.8
-12.7
-12.5
-12.4
-12.3
-12.1
-12
-11.8
86.35
85.96
85.57
85.18
84.79
84.40
84.01
83.62
83.23
82.84
82.45
82.06
81.67
81.27
80.88
80.49
80.10
79.71
79.32
78.93
78.54
78.15
77.76
77.37
76.98
76.59
76.20
75.81
75.42
75.02
74.63
74.24
Continued
© 2009 IXYS Corp.
Characteristics subject to change without notice
20
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Table 10 Dynamic Mode Dimming in Logarithmic Mode vs. register 05h data
# of steps
Hex code
Dimming,
dB
Dimming,
%
# of steps
Hex code
Dimming,
dB
Dimming,
%
Continue
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
-11.6
-11.3
-11.1
-10.9
-10.6
-10.4
-10.2
-10
-9.8
-9.5
-9.3
-9.2
-9
-8.8
-8.6
-8.4
-8.2
-8.1
-7.9
-7.7
-7.6
-7.4
-7.3
-7.1
-6.9
-6.8
-6.7
-6.5
-6.4
-6.2
-6.1
-6
73.46
72.68
71.90
71.12
70.34
69.56
68.77
67.99
67.21
66.43
65.65
64.87
64.09
63.31
62.52
61.74
60.96
60.18
59.40
58.62
57.84
57.06
56.27
55.49
54.71
53.93
53.15
52.37
51.59
50.81
50.02
49.24
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
-5.7
-5.4
-5.2
-4.9
-4.7
-4.5
-4.3
-4
-3.8
-3.6
-3.4
-3.2
-3
-2.8
-2.7
-2.5
-2.3
-2.1
-2
-1.8
-1.6
-1.5
-1.3
-1.2
-1
-0.8
-0.7
-0.6
-0.4
-0.3
-0.1
0
47.68
46.12
44.56
42.99
41.43
39.87
38.31
36.74
35.18
33.62
32.06
30.49
28.93
27.37
25.81
24.24
22.68
21.12
19.56
17.99
16.43
14.87
13.31
11.74
10.18
8.62
7.06
5.49
3.93
2.37
0.81
0.00
© 2009 IXYS Corp.
Characteristics subject to change without notice
21
Doc. No. 8141/61_DS, Rev. N1.0
LDS8161/41
Warranty and Use
IXYS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY
PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD
PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH
USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
IXYS Corp. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the IXYS Corp. product could create a situation where personal injury or death may occur.
IXYS Corp. reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance
Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
IXYS Corp. advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor
applications and may not be complete.
IXYS Corp.
1590 Buckeye Dr.,
Milpitas, CA 95035-7418
Phone: 408.457.9000
Fax:
408.496.0222
http://www.ixys.com
© 2009 IXYS Corp.
Characteristics subject to change without notice
Document No: 8141/61_DS
Revision:
N1.0
Issue date:
10/20/2009
22
Doc. No. 8141/61_DS, Rev. N1.0
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