CLA40MT1200NPZ

CLA40MT1200NPZ High Efficiency Thyristor VRRM = 1200 V I TAV = 20 A VT = 1.37 V Three Quadrants operation: QI - QIII 1~ Triac Part number CLA40MT1200NPZ Marking on Product: CLA40MT1200NPZ Backside: anode/cathode Three Quadrants Operation T2 Positive Half Cycle + (-) IGT T2 (+) IGT T1 REF IGT - 4 T2 T1 QII QI QIII QIV REF + IGT (-) IGT 3 1 T1 REF Negative Half Cycle Note: All Polarities are referenced to T1 Features / Advantages: Applications: Package: TO-263 (D2Pak-HV) ● Triac for line frequency ● Three Quadrants Operation - QI - QIII ● Planar passivated chip ● Long-term stability of blocking currents and voltages ● Line rectifying 50/60 Hz ● Softstart AC motor control ● DC Motor control ● Power converter ● AC power control ● Lighting and temperature control ● Industry standard outline ● RoHS compliant ● Epoxy meets UL 94V-0 ● High creepage distance between terminals Disclaimer Notice Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications. Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics. IXYS reserves the right to change limits, conditions and dimensions. © 2020 IXYS all rights reserved Data according to IEC 60747and per semiconductor unless otherwise specified 20200121d CLA40MT1200NPZ Ratings Rectifier Conditions Symbol VRSM/DSM Definition max. non-repetitive reverse/forward blocking voltage TVJ = 25°C VRRM/DRM max. repetitive reverse/forward blocking voltage TVJ = 25°C I R/D reverse current, drain current VT forward voltage drop 10 µA 1.5 mA TVJ = 25°C 1.37 V 1.71 V 1.37 V IT = 20 A IT = 40 A IT = 20 A IT = 40 A I RMS 180° sine VT0 threshold voltage rT slope resistance R thJC thermal resistance junction to case TVJ = 125 °C for power loss calculation only total power dissipation I TSM max. forward surge current value for fusing V TVJ = 25°C RMS forward current per phase thermal resistance case to heatsink 1200 TVJ = 125°C TC = 115 °C RthCH max. Unit 1300 V VR/D = 1200 V average forward current Ptot typ. VR/D = 1200 V I TAV I²t min. 1.83 V T VJ = 150 °C 20 A 44 A TVJ = 150 °C 0.89 V 24 mΩ 0.8 K/W 0.3 K/W TC = 25°C 155 W t = 10 ms; (50 Hz), sine TVJ = 45°C 200 A t = 8,3 ms; (60 Hz), sine VR = 0 V 215 A t = 10 ms; (50 Hz), sine TVJ = 150 °C 170 A t = 8,3 ms; (60 Hz), sine VR = 0 V 185 A t = 10 ms; (50 Hz), sine TVJ = 45°C 200 A²s t = 8,3 ms; (60 Hz), sine VR = 0 V 190 A²s t = 10 ms; (50 Hz), sine TVJ = 150 °C 145 A²s 140 A²s t = 8,3 ms; (60 Hz), sine VR = 0 V CJ junction capacitance VR = 400 V f = 1 MHz TVJ = 25°C PGM max. gate power dissipation t P = 30 µs T C = 150 °C 12 t P = 300 µs PGAV average gate power dissipation (di/dt) cr critical rate of rise of current TVJ = 150 °C; f = 50 Hz repetitive, IT = t P = 200 µs; di G /dt = 0.3 A/µs; 60 A IG = 20 A (dv/dt)cr critical rate of rise of voltage V = ⅔ VDRM VGT gate trigger voltage I GT gate trigger current VGD gate non-trigger voltage I GD gate non-trigger current IL latching current 0.3 A; V = ⅔ VDRM non-repet., I T = pF 5 W 1 W 0.2 W 150 A/µs 500 A/µs TVJ = 150°C 500 V/µs VD = 6 V TVJ = 25 °C 1.3 TVJ = -40 °C 1.6 V VD = 6 V TVJ = 25 °C ± 40 mA TVJ = -40 °C ± 60 mA TVJ = 150°C 0.2 V ±1 mA TVJ = 25 °C 70 mA R GK = ∞; method 1 (linear voltage rise) VD = ⅔ VDRM tp = 10 µs IG = 0.3 A; di G /dt = V 0.3 A/µs IH holding current VD = 6 V R GK = ∞ TVJ = 25 °C 50 mA t gd gate controlled delay time VD = ½ VDRM TVJ = 25 °C 2 µs tq turn-off time IG = 0.3 A; di G /dt = VR = 100 V; I T = 0.3 A/µs 20A; V = ⅔ VDRM TVJ =125 °C di/dt = 10 A/µs dv/dt = IXYS reserves the right to change limits, conditions and dimensions. © 2020 IXYS all rights reserved 150 µs 20 V/µs t p = 200 µs Data according to IEC 60747and per semiconductor unless otherwise specified 20200121d CLA40MT1200NPZ Package Ratings TO-263 (D2Pak-HV) Symbol I RMS Definition Conditions RMS current per terminal min. TVJ virtual junction temperature T op operation temperature Tstg storage temperature -40 typ. max. 35 Unit A -40 150 °C -40 125 °C 150 °C 1.5 Weight FC 20 mounting force with clip d Spp/App Product Marking C L A 40 MT 1200 N PZ IXYS yywwZ Logo Date Code Location N 4.2 mm terminal to backside 4.7 mm Part description XXXXXXXXX Part Number 60 terminal to terminal creepage distance on surface | striking distance through air d Spb/Apb g 123456 = = = = = = = = Thyristor (SCR) High Efficiency Thyristor (up to 1200V) Current Rating [A] 1~ Triac Reverse Voltage [V] Three Quadrants operation: QI - QIII TO-263AB (D2Pak) (2HV) Lot# Ordering Standard Alternative Ordering Number CLA40MT1200NPZ-TRL CLA40MT1200NPZ-TUB Similar Part CLA40MT1200NPB Equivalent Circuits for Simulation I V0 R0 Package TO-220AB (3) * on die level Delivery Mode Tape & Reel Tube Quantity 800 50 Code No. 515974 525269 Voltage class 1200 T VJ = 150°C Thyristor V 0 max threshold voltage 0.89 R0 max slope resistance * 21 IXYS reserves the right to change limits, conditions and dimensions. © 2020 IXYS all rights reserved Marking on Product CLA40MT1200NPZ CLA40MT1200NPZ V mΩ Data according to IEC 60747and per semiconductor unless otherwise specified 20200121d CLA40MT1200NPZ Outlines TO-263 (D2Pak-HV) Dim. W Supplier Option D1 L1 c2 A1 H D E A 1 4 3 L e1 D2 A2 c 2x e 2x b2 10.92 (0.430) W E1 Inches min max 0.160 0.190 typ. 0.004 0.095 0.020 0.039 0.045 0.055 0.016 0.029 0.045 0.055 0.330 0.370 0.315 0.350 0.091 0.380 0.410 0.245 0.335 0,100 BSC 0.169 0.575 0.625 0.070 0.110 0.040 0.066 typ. 0.002 0.0008 All dimensions conform with and/or within JEDEC standard. 1.78 (0.07) 3.05 (0.120) 3.81 (0.150) 9.02 (0.355) mm (Inches) 2x b A A1 A2 b b2 c c2 D D1 D2 E E1 e e1 H L L1 Millimeter min max 4.06 4.83 typ. 0.10 2.41 0.51 0.99 1.14 1.40 0.40 0.74 1.14 1.40 8.38 9.40 8.00 8.89 2.3 9.65 10.41 6.22 8.50 2,54 BSC 4.28 14.61 15.88 1.78 2.79 1.02 1.68 typ. 0.040 0.02 2.54 (0.100) Recommended min. foot print 4 3 1 IXYS reserves the right to change limits, conditions and dimensions. © 2020 IXYS all rights reserved Data according to IEC 60747and per semiconductor unless otherwise specified 20200121d CLA40MT1200NPZ Thyristor 40 160 TVJ = 125°C 30 IT 1000 50 Hz, 80% VRRM TVJ = 150°C VR = 0 V 140 120 2 It TVJ = 45°C ITSM 20 2 100 [A] TVJ = 45°C 100 [A s] TVJ = 125°C [A] 10 80 TVJ = 125°C TVJ = 25°C 0 0,5 60 1,0 1,5 2,0 10 2,5 0,01 0,1 VT [V] Fig. 1 Forward characteristics 4 1 IGD: TVJ = -40°C IGD: TVJ = 25°C 2 [V] IGD: TVJ = 0°C B B 2 3 4 5 6 7 8 910 t [s] t [ms] Fig. 2 Surge overload current Fig. 3 I t versus time (1-10 ms) 2 40 dc = 1 0.5 0.4 0.33 0.17 0.08 C B VG 1 1000 IGD: TVJ = 125°C 3 1 30 100 typ. tgd IT(AV)M Limit 20 [µs] [A] 10 TVJ = 125°C 10 IGD: TVJ = 25°C A 1 10 0 0 25 50 75 0 100 1000 0 25 IG [mA] IG [mA] 75 100 125 150 175 TC [°C] Fig. 5 Gate controlled delay time Fig. 4 Gate trigger characteristics 50 Fig. 6 Max. forward current at case temperature 1,0 dc = 40 1 0.5 0.4 0.33 30 0.17 0.08 RthHA 0.4 0.6 0.8 1.0 2.0 4.0 0,8 ZthJC 0,6 P(AV) [K/W] 20 Rthi [K/W] 0,4 [W] 10 0,2 0 0 10 20 IT(AV) [A] 0 50 100 0,0 100 150 Tamb [°C] © 2020 IXYS all rights reserved 102 0.0100 0.0011 0.20 0.21 0.21 0.0250 0.3200 0.0900 103 104 t [ms] Fig. 7a Power dissipation versus direct output current Fig. 7b and ambient temperature IXYS reserves the right to change limits, conditions and dimensions. 101 ti [s] 0.10 0.08 Fig. 8 Transient thermal impedance Data according to IEC 60747and per semiconductor unless otherwise specified 20200121d