NCD2400MTR

NCD2400M Wide Capacitance Range, Non-volatile Digital Programmable Capacitor INTEGRATED CIRCUITS DIVISION Features Description • DC to 150MHz frequency range • 512-state digital programmable capacitor • Series or shunt configuration Cshunt = 12.5pF to 194pF (15.5:1 tuning ratio) in discrete 355fF steps Cseries = 1.7pF to 194pF in discrete 376fF steps The NCD2400M is a dedicated electronic calibrator for oscillators, with reliable performance at 105ºC as required by OCXO applications. • • • • • This product can be used in series or shunt configuration to support a wide variety of tuning circuit topologies. 2-wire (I2C Fast-mode compatible) serial interface EEPROM non-volatile memory Wide power supply range (2.5V to 5.5V) Operation ambient temperature to 105ºC 2 x 2 x 0.65 mm 6-pin DFN package Digitally controlled capacitance trimming information is communicated via a 2-wire, I2C Fast-mode compatible interface. The preferred power-up default capacitance value can be stored in the internal, re-programmable, non-volatile memory. Applications • • • • • • Ordering Information OCXOs Oscillators Tunable RF stages Filter tuning Capacitive sensor trimming Measurement equipment Part # Description NCD2400MTR Standard product, Chip ID = 0x60, DFN-6 in Tape & Reel (3000/Reel) NCD2400M1TR Special order, Contact Factory for details, Chip ID = 0x61, DFN-6 in Tape & Reel (3000/Reel) Figure 1. NCD2400M Block Diagram VDD V+ NCD2400M V+ CP SDA V+ DIGITAL INTERFACE AND MEMORY C0 SCL CN GND DS-NCD2400M-R01 www.ixysic.com 1 NCD2400M INTEGRATED CIRCUITS DIVISION 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 General Conditions for Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Capacitor Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Digital Interface: Electrical Characteristics of SDA and SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Digital Interface: AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 3 4 4 5 5 5 2. Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Capacitive Digital to Analog Converter (CDAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Non-Volatile Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Volatile Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Non-Volatile Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 I2C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Write Volatile Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Write Non-Volatile Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 Set Non-Volatile Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Electrical and Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Capacitor Interface Electrical and Biasing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 13 13 13 13 13 14 14 15 17 18 19 19 19 4. Capacitance Determination and Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Tape & Reel Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.ixysic.com 21 21 21 21 21 22 22 22 R01 NCD2400M INTEGRATED CIRCUITS DIVISION 1. Specifications 1.1 Package Pinout 1.3 Absolute Maximum Ratings SDA 1 6 SCL CP 2 5 GND CN 3 4 VDD Parameter Supply voltage SDA, SCL voltage CP voltage CN voltage VDD < 3.3V VDD > 3.3V Operating temperature, TA Storage temperature, TSTG 1.2 Pin Descriptions Pin Name 1 2 3 4 5 6 SDA CP CN VDD GND SCL Description Minimum Maximum Unit -0.3 +6 V VDD + 0.3 V -0.3 VDD + 0.5 V -0.5 -0.5 -40 -55 VDD + 0.5 3.8 +105 +125 V C C Absolute maximum voltages are with respect to GND. Serial data I/O Positive capacitance node Negative capacitance node Power supply Ground Serial clock input Absolute maximum electrical ratings are over the operating temperature range. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 Recommended Operating Conditions Parameter Supply voltage Capacitor voltage, CP or CN to GND 1, 2 VDD < 3.3V VDD > 3.3V Non-Volatile Write Programming time 3 Operating temperature Symbol Minimum Typical Maximum Unit VDD 2.5 3.3 5.5 V VCP, VCN -0.3 - tPNV - 5 - ms TA -40 - +105 °C VDD + 0.3 VPK 3.6 1 VPK=VDC+VAC is the voltage applied to capacitor pins CP and CN. It should never exceed 3.6V in operation, and should never be less than -0.3V. Sufficient DC bias must be applied to the capacitor pins to prevent the AC signal from violating this specification. Pins CP and CN are not self biased. 2 These maximum values not to exceed the supply voltage; e.g. the maximum voltage drop between CN and GND is 2.8V when V =2.5V. DD 3 There are three erase commands and three non-volatile write commands to program the Non-Volatile Register. This time is for each of the three non-volatile write commands, not the sum of all three commands. The timing requirement also applies to each of the three erase commands, not the sum of all three. 1.5 ESD Rating Parameter Human body model Charge device model R01 Symbol Conditions Rating Unit HBM CDM EIA/JESD22-A114-D JS002-2014 +2000 +500 V www.ixysic.com 3 NCD2400M INTEGRATED CIRCUITS DIVISION 1.6 General Conditions for Electrical Characteristics Typical values are the result of engineering evaluations and are characteristic of the device at 25°C with VDD=3.3V and pins CP and CN biased to 1.65VDC. They are provided for informational purposes only and are not guaranteed by production testing. Unless otherwise specified, specifications cover the operating temperature range TA=-40ºC to +105ºC, and the supply voltage range VDD= 2.5V to 5.5V. 1.7 Capacitor Electrical Characteristics Unless otherwise noted, characteristics are at the nominal operating temperature of 25 ±5°C with the CP and CN terminals biased at one-half of the supply voltage. Parameter Operating frequency range Capacitance, Series Configuration Minimum Maximum Minimum Maximum 1 Maximum Unit - 150 MHz C0 1.6 1.7 1.9 Code=511 f=50MHz Code=0 C511 177.3 194 209.2 C0 1.6 1.7 1.9 Code=511 C511 181.4 202.2 221.3 pF C0 11.5 12.5 13.5 C511 178.4 193.9 209.4 C0 11.5 12.5 13.9 Code=511 Cmax / Cmin, f=10MHz C511 188.8 203.0 229 - - 15.512:1 - - Constant step size at f=10MHz f=10MHz Code=0 Cstep - 376.32 - fF QC0 - >150 - Code=511 f=50MHz Code=0 QC511 35 95 - QC0 - 43 - Code=511 QC511 6.6 18.5 - -40°C < TA < +105°C, f=10MHz dC/dT - 250 680 Maximum Tuning ratio, Shunt Configuration 4 Typical - Code=0 Minimum 1 Minimum - Code=511 f=50MHz Code=0 Maximum Capacitance variation with temperature Symbol f=10MHz Code=0 f=10MHz Capacitance, Shunt Configuration Minimum Step size, Series Configuration Quality Factor Test Conditions - ppm/°C Shunt configuration: CP to Grounded CN www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 1.8 Digital Interface: Electrical Characteristics of SDA and SCL Parameter Test Conditions Symbol Minimum Typical Maximum Unit - VIH 0.75VDD - VIH - VIL VIL - - 0.25VDD V VHYS 0.1 - - VOH 0.95VDD - - VOL - - 0.4 111 135 154 88 135 186 Input voltage Logic 1 threshold Logic 0 threshold Hysteresis SDA Output voltage 1 Logic 1 10k pull-up resistor IOL = 6mA Logic 0 TA=25°C Pull-up resistors, Internal RPU -40°C < TA < +105°C Load capacitance CLOAD - V k 400 pF 1 SDA is an open drain pad. It is recommended to use a pull-up resistor with a value such that the current into pin SDA does not exceed 6mA, independent of the internal pull-up resistors. 1.9 Digital Interface: AC Characteristics Parameter Symbol Serial clock (SCL) Frequency Duty cycle Rise / fall times Minimum Typical Maximum Unit fSCL - - 400 kHz DSCL 40 - 60 % ns tR / tF - - 100 Serial data (SDA) Setup time tsetup 300 - - Rise / fall times tR / tF - - 100 tVD,DAT - - 180 ns tPNV 4 8 ms Data valid time1 Non-Volatile Write Programming time 2, 3 ns 1 RP = 1k, CLOAD = 100pF Programming time begins with the falling edge of CLK just after the CONFIG 0 ACK and ends with the rising Stop bit edge on SDA. 3 This time is for each non-volatile write commands, not the sum of all three commands. 2 S Chip ID + W A CONFIG 1 A CONFIG 0 A WAIT A A ... WAIT WAIT A P Programming Time tR tF tsetup SDA SCL Stable Data Line SDA Valid Data Transitions Allowed tVD,DAT Note: SDA output transitions occur only when SCL is low, as shown in the following timing diagram. 1.10 Power Supply Parameter Supply voltage Supply current R01 Symbol Minimum Typical Maximum Unit VDD IDD 2.5 - 3.3 50 5.5 90 V A www.ixysic.com 5 NCD2400M INTEGRATED CIRCUITS DIVISION 2. Performance Data Note: The performance data shown in the graphs below is the measured performance at ambient temperature. The typical shunt and series capacitance, in pF, varies as indicated in the following equations: C OUT = C 0 + C var C shunt = 12.5 + 0.355  Code C series = 1.7 + 0.376  Code Where Code = 0 to 511. Other performance aspects of the programmable capacitor are illustrated in the graphs below. Figure 1: Shunt and Series Capacitance vs. Code Capacitance vs. State (f=10MHz) Capacitance (pF) 200 150 100 Cshunt Cseries 50 0 0 100 200 300 400 500 600 Code In shunt configuration, the parasitic capacitance from pin CP to GND adds up to the total equivalent capacitance of the device. The expected values are the ones defined by the above equation. In series configuration, though, this parasitic capacitor is not part of the equivalent impedance of the device, therefore the overall capacitance seen between CP and CN is smaller. 6 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION Figure 2: Series Capacitance vs. Frequency for Code 64 to Code 511 Capacitance vs. Frequency Code 64 to Code 511 250 C511 Capacitance (pF) 200 150 C256 100 C128 50 C64 0 0 20 40 60 80 Frequency (MHz) 100 120 Figure 3: Series Capacitance vs. Frequency for Code 0 to Code 64 Capacitance vs. Frequency Code 0 to Code 64 30 Capacitance (pF) C64 20 C32 C16 C8 C4 C2 C1 C0 10 0 0 R01 20 40 60 80 Frequency (MHz) www.ixysic.com 100 120 7 NCD2400M INTEGRATED CIRCUITS DIVISION Figure 4: Quality Factor vs. Frequency and Code Quality Factor vs. Frequency Quality Factor 1000 100 C32 C64 C128 C256 C511 10 1 0 20 40 60 80 100 120 Frequency (MHz) Figure 5: ESR vs. Code for Nominal Operation Conditions ESR (Ω) Equivalent Series Resistance (ESR) (f=10MHz) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 8 50 100 150 200 250 300 350 400 450 500 Code www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION The figure below shows how the capacitance varies with the supply voltage while CN is biased at one-half of the supply voltage level. Here, the value obtained for 3.3V is used as a reference and the deviation is given in percentage. Please note that for VDD > 3.6V no further variations are expected. Figure 6: Variation of the Capacitance at 10MHz with Supply Voltage, Relative to the Value at 3.3V Capacitance Variation (%) Capacitance Variation vs. Supply Voltage Relative to 3.3V (f=10MHz) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 C0 C1 C2 C4 C8 C16 C32 C64 C128 C256 C511 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) DC voltage biasing of the CN terminal has a small though visible influence on the performance of the Digital Programmable Capacitor. The table below presents the variation of the series capacitance and ESR at 10MHz when pin CN is biased at 0V, 1.65V and 3.3V, with VDD=3.3V. DC bias applied to pin CP has no affect on the capacitance or ESR values. Capacitance (pF) R01 ESR () Code / Vbias (V) 0 1.65 3.3 0 1.65 3.3 0 1.7 1.7 1.9 0.509 0.442 0.695 1 2.1 2.1 2.3 0.739 0.720 1.006 2 2.5 2.5 2.7 0.949 0.973 1.29 4 3.2 3.2 3.5 1.271 1.366 1.742 8 4.7 4.7 5.1 1.754 1.952 2.431 16 7.6 7.7 8.2 2.256 2.564 3.188 32 13.7 13.7 14.3 4.342 4.968 6.31 64 25.6 25.6 26.4 3.259 3.755 4.882 128 49.6 49.6 50.3 2.063 2.372 3.14 256 97.4 97.5 98.1 1.204 1.377 1.827 511 193.2 194 193.2 0.75 0.846 1.106 www.ixysic.com 9 NCD2400M INTEGRATED CIRCUITS DIVISION The equivalent shunt capacitance changes for small variations of the supply voltage around the nominal value. The following table shows the deviation of the equivalent shunt capacitance for a 200mV change of the supply voltage from 3.3V. Relative deviation of the capacitance with respect to the supply voltage around nominal value of 3.3V. Parameter Code 0 Code 1 Code 2 Code 4 Code 8 pF/V -0.22 -0.22 -0.22 -0.22 -0.22 Code 16 Code 32 Code 64 Code 128 Code 256 Code 511 -0.21 -0.21 -0.19 -0.17 -0.11 -0.01 For a deviation of +200mV in supply voltage, the capacitance for Code 0 will be modified by -0.044pF. Using the previously-stated equation for calculating the nominal values of Cshunt it can be expected the nominal value of Cshunt will shift from 12.5pF to 12.456pF. Similarly, for a supply voltage change of -200mV, the nominal value of Cshunt will be 12.5pF - (-0.044pF) = 12.544pF. 10 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 3. Functional Description 3.1 Introduction The NCD2400M provides a digitally controlled variable output capacitance between pins CP and CN. This capacitance can be used as a series capacitor (between CP and CN) or a shunt capacitor (connecting CN to GND). Do not connect CP to GND. The output capacitance is set by either the content of the Volatile Register or by the content stored in the re-programmable Non-Volatile Memory. Upon power-up, the default capacitance value between CP and CN is determined by the digital value stored in the non-volatile memory. The capacitance can, however, be controlled directly with the content of the Volatile Register. The output capacitance presented by the NCD2400M between pins CP and CN is defined by: The NCD2400M has two operating modes related to the way the programmable capacitor is controlled: Volatile and Non-Volatile. • Volatile Mode: the Control Data value in the Volatile Register determines the output capacitance. • Non-Volatile Mode (Default mode): the Control Data value stored in the Non-Volatile Memory determines the output capacitance. In Non-Volatile Mode, the default mode, the Control Data value is determined by the content programmed into the non-volatile memory. This mode is useful in situations where the required output capacitance is unlikely to change and the control data must be retained during periods of no power. COUT = C0 + Cvar Where: • C0 is the base output capacitance (Code 0) and • Cvar is the variable tuning capacitance, whose value is set by the 9-bit CDAC control word R01 www.ixysic.com 11 NCD2400M INTEGRATED CIRCUITS DIVISION 3.2 Capacitive Digital to Analog Converter (CDAC) The nine bits in the Capacitive Digital to Analog Converter constitute the control bits of the variable capacitor. Shown in the table below are the expected typical capacitance values of several codes for the series configuration. Decimal Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COUT (pF) 0 0 0 0 0 0 0 0 0 0 1.70 1 0 0 0 0 0 0 0 0 1 2.08 2 0 0 0 0 0 0 0 1 0 2.45 3 0 0 0 0 0 0 0 1 1 2.83 4 0 0 0 0 0 0 1 0 0 3.20 5 0 0 0 0 0 0 1 0 1 3.58 6 0 0 0 0 0 0 1 1 0 3.96 12 7 0 0 0 0 0 0 1 1 1 4.33 125 0 0 1 1 1 1 1 0 1 48.70 126 0 0 1 1 1 1 1 1 0 49.08 127 0 0 1 1 1 1 1 1 1 49.45 128 0 1 0 0 0 0 0 0 0 49.83 250 0 1 1 1 1 1 0 1 0 95.70 251 0 1 1 1 1 1 0 1 1 96.08 252 0 1 1 1 1 1 1 0 0 96.45 253 0 1 1 1 1 1 1 0 1 96.83 254 0 1 1 1 1 1 1 1 0 97.20 255 0 1 1 1 1 1 1 1 1 97.58 256 1 0 0 0 0 0 0 0 0 97.96 499 1 1 1 1 1 0 0 1 1 189.32 500 1 1 1 1 1 0 1 0 0 189.70 501 1 1 1 1 1 0 1 0 1 190.08 502 1 1 1 1 1 0 1 1 0 190.45 503 1 1 1 1 1 0 1 1 1 190.83 504 1 1 1 1 1 1 0 0 0 191.20 505 1 1 1 1 1 1 0 0 1 191.58 506 1 1 1 1 1 1 0 1 0 191.96 507 1 1 1 1 1 1 0 1 1 192.33 508 1 1 1 1 1 1 1 0 0 192.71 509 1 1 1 1 1 1 1 0 1 193.08 510 1 1 1 1 1 1 1 1 0 193.46 511 1 1 1 1 1 1 1 1 1 193.84 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 3.3 Non-Volatile Memory Configuration The 9-bit CDAC code stored in non-volatile memory is organized in three addressable nibbles as shown below: NON-VOLATILE MEMORY MAP Address 0x2 Anytime data is written into the Volatile Register, Volatile Mode is automatically enabled and remains active until a loss of power or the “Set Non-Volatile Mode” command is received. The contents of the volatile register will be lost whenever power to the device is removed. NV 3.5.2 Non-Volatile Mode Address 0x1 NV Address 0x0 NV Non-Volatile Mode is the default mode of operation and uses the value stored in the Non-Volatile memory (NV) to configure the capacitor. 3.4 Device Address NCD2400M has two available 7-bit device addresses (Chip ID) hard-coded during manufacturing. These are shown in the table below. Address Selection Model Address (HEX) Address (BIN) Address (DEC) NCD2400M 0x60 1100000 96 NCD2400M1 0x61 1100001 97 Non-Volatile Mode is entered into automatically at power up, or after receiving the “Set Non-Volatile Mode” command. 3.6 I2C Serial Interface This simple way of addressing allows for easy configuration in systems that employ up to two NCD2400M slaves. 3.5 Operating Modes The NCD2400M functions in one of two modes, Volatile and Non-Volatile. The output capacitance between CP and CN can be controlled by the value loaded into the volatile register (Volatile Mode), or by reading the value stored in the non-volatile memory (Non-Volatile Mode). 3.5.1 Volatile Mode Volatile Mode provides the means to alter the output capacitance at any time. Because Volatile Mode is functional over the entire operational range of the NCD2400M, the capacitance presented between CP and CN can be modified under all allowed operating conditions. Modifying the capacitance in Volatile Mode is easily accomplished by writing the 9-bit CDAC control code into the Volatile Register (VR), using the I2C interface. R01 By default, upon power up, the NCD2400M operates in the Non-Volatile Mode. This is advantageous for applications where reprogramming the capacitance value is not convenient or for applications where the end product may be subjected to an unreliable power environment. The NCD2400M digitally controlled variable capacitor can be accessed by an I2C serial interface. The NCD2400M can only act as a Bus Slave. The Bus Master initiates the start of a serial transaction by driving SDA (Serial Data) low while SCL (Serial Clock) is high. This is the Start bit. Data bit transitions on SDA are permitted only when SCL is low and are clocked in by the receiver on the rising edge of SCL. A logic low (0) Acknowledge (ACK) bit is output onto the SDA bus by the NCD2400M following each received byte. Depending on the value of the Read/Write (R/W) bit following the 7-bit device address (Chip ID), a read or write command will be executed. Four operations are available through the serial interface: • • • • www.ixysic.com Write Volatile Register Write Non-Volatile Memory Read Set Non-Volatile Mode 13 NCD2400M INTEGRATED CIRCUITS DIVISION 3.6.1 Write Commands With a valid device address and the R/W bit set to 0, the NCD2400M will execute a write operation. The 8-bit address byte follows the Start bit and consists of two parts, first the device 7-bit Chip ID then the R/W bit located in the byte’s least significant bit (LSB) position. For a given device Chip ID, the address byte is the same for all write commands. CONFIG 1 consists of the NV/V control bit, six Don’t Care bits, and the MSB of the CDAC code to be written into the Volatile Register. Setting NV/V = 1 specifies a Non-Volatile Memory write operation and when NV/V = 0, a Volatile Register write operation will be executed. The most significant bit (MSB) of CONFIG 1, CONFIG 1 is the NV/V control bit. For a Volatile Register write the next six bits, CONFIG 1 , are Don’t Care bits while the last bit, CONFIG 1 is the MSB of the CDAC code being written. Following the device address byte, for all write commands, the Master will send two CONFIG data bytes containing information to control the device and when the output capacitor value is to be modified, CDAC codes. As with the address byte, both CONFIG 1 and CONFIG 0 are 8-bit bytes. Located between the NV/V and CDAC MSB bits are the six Don’t Care bits. Their value has no effect on the outcome of the Volatile Register write operation. Since a logic 0 on an I2C bus is the dominant state, it is recommended these six bits be set to 0 in applications where the bus is shared with other devices or where the unit is located in a noisy environment. The three realizable operations by means of the write command are: • Write Volatile Register • Write Non-Volatile Memory • Set Non-Volatile Mode The nine bit CDAC data to be written into the volatile register is contained within the two Configuration Bytes as such: 3.6.2 Write Volatile Register Operation The Write Volatile Register Operation takes data from the Configuration Bytes and stores it in the Volatile Register. Additionally, anytime the Write Volatile Register Operation is executed, the NCD2400M will be placed into the Volatile Mode. In order to return to the Non-Volatile Mode the device will need to be power cycled or sent a “Set Non-Volatile Mode” command • CDAC bit is the last bit (LSB) of CONFIG 1 • CDAC bits are the CONFIG 0 bits. The CDAC bits map directly to the Volatile Register such that CDAC = VR, CDAC = VR, and so on. The data transfer format for writing to the Volatile Register (NV/V = 0) is shown below for a device with Chip ID 0x60. A Write Volatile Register command issued by the bus Master consists of the device address byte followed by two CONFIG byte sequences: CONFIG 1 then CONFIG 0. WRITE OPERATION: VOLATILE REGISTER S Chip ID + W Chip ID + W 1 1 0 A CONFIG 1 0 0 A CONFIG 0 0 7-Bit Address CONFIG 1 0 x x x x x A P 0 0 a R/W x VR Master to Slave Slave to Master NV / V CONFIG 0 VR NOTE: In the diagram above, bit “a” in the address byte is the LSB of the Chip ID. Set this bit to 1 when addressing the NCD2400M1 device as its Chip ID address is 0x61. 14 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 3.6.3 Write Non-Volatile Memory Operation A Write Non-Volatile Operation takes data from the Configuration Bytes and stores it in the Non-Volatile Memory. Unlike the Write Volatile Register Operation, the Write Non-Volatile Operation does not change the operating mode of the device. Therefore, a Write Non-Volatile Memory Operation may be performed while the device is operating in either the Volatile or the Non-Volatile mode. Although the CDAC code stored in the non-volatile memory is nine bits, the same as the Volatile Register, programming the non-volatile memory requires a write command for each addressable memory nibble. Furthermore, each nibble must be erased before being written. The data structure of the two CONFIG bytes is the same for all three memory nibbles. CONFIG 1 contains the NV/V control bit, the two bit memory nibble address, the “Set Non-Volatile Mode” control bit, and four Don’t Care bits. CONFIG 0 contains the CDAC data bits preceded by sufficient Don’t Care bits to fill the byte. For an erase operation, CONFIG 0 is always four Don’t Care bits followed by 0x0. In CONFIG 1 (MSB), setting NV/V = 1 selects writing the incoming data to the Non-Volatile Memory. Following the NV/V bit in CONFIG 1 are the two non-volatile memory address bits, then the Set Non-Volatile Mode control bit and four Don’t Care bits to complete the byte. The two bit non-volatile memory address MSB is placed in CONFIG 1 with the LSB following in CONFIG 1 . In CONFIG 1 is the Set Non-Volatile Mode control bit which must be set to a logic 0 for a non-volatile write command. The last four bits, CONFIG are Don’t Care bits. The 9-bit CDAC data to be written into the non-volatile memory is embedded within the CONFIG 0 byte across three write commands. Shown in the table below is the data structure of the three CONFIG 1 and CONFIG 0 bytes required to program a new 9-bit CDAC code into the non-volatile memory or to erase the memory. Lower case “x” in CONFIG 1 and CONFIG 0 indicates a Don’t Care bit value. MEMORY ADDRESS CONFIG 1 CDAC DATA CONFIG 0 ERASE CONFIG 0 0x2 1100 xxxx xxxxxxx CDAC xxxx 0000 0x1 1010 xxxx xxxx CDAC xxxx 0000 0x0 1000 xxxx xxxx CDAC xxxx 0000 R01 The CDAC bits map directly to the Non-Volatile Memory such that CDAC = NV, CDAC = NV, and so on. The three addressable Non-Volatile Memory nibbles may be treated as independent entities. This means they may be written in any order and do not all have to be written to update the value stored in memory. If desired, just one or two can be updated, leaving the non-updated nibbles at their current value. The duration of each non-volatile write operation must satisfy the Non-Volatile Write Programming time specified in Section 1.4 "Recommended Operating Conditions” on page 3. The programming time is defined as the period from the falling CLK edge just after the CONFIG 0 ACK bit output by the NCD2400M until the rising Stop bit edge on SDA output by the bus master. In the example below, WAIT bytes are sent on the SDA data bus for the programming time duration. Using WAIT bytes with value 0x00 prevents other devices on the bus or noise from interfering with the NCD2400M internal programming process. Alternatively, in a well controlled environment the WAIT bytes need not be applied. Holding CLK, the serial clock, low (Logic 0) to lock up the I2C bus to satisfy the programming time duration is acceptable. A Stop bit is required to terminate the programming time duration, ending the NCD2400M internal programming procedure. Failure to comply with the programming time requirements may result in failure of the non-volatile memory to retain its stored information or damage to the device. Following the Non-Volatile Write sequence, a Read command or a power up reset must be executed to update the contents of the CDAC non-volatile control register with the new memory value. If the NCD2400M is operating in the Volatile Mode during the Non-Volatile write operation, then a “Set Non-Volatile Mode” command must be executed after the Read command for the programmable capacitor value to reflect the new memory value. www.ixysic.com 15 NCD2400M INTEGRATED CIRCUITS DIVISION Prior to writing new data into the non-volatile memory the existing data must be erased. The erase operation is a non-volatile write with CONFIG 0 = xxxx0000. A Read command is not required following an erase operation unless the change is to set the memory nibble(s) value to 0x0. In the programming example below, the three memory nibbles are being written with address 0x2 first and 0x0 last. The logical structure of a Write Non-Volatile Memory Operation is provided in the diagram below. WRITE OPERATION: NON-VOLATILE MEMORY S Chip ID + W A CONFIG 1 A CONFIG 0 A WAIT A WAIT A ... WAIT A P Programming Time Chip ID + W 1 1 0 0 0 0 0 0 a R/W 7-Bit Address CONFIG 1 1 NV / V 1 0 NV Memory Address 0 x x x x x x x x x x x NV WAIT x x x x x x x x CONFIG 1 A Slave to Master Set NV Mode CONFIG 0 S Chip ID + W A Master to slave CONFIG 0 A WAIT A WAIT A ... WAIT A P Programming Time Chip ID + W 1 1 0 0 0 0 0 0 a R/W x x 7-Bit Address CONFIG 1 1 NV / V 0 1 NV Memory Address 0 x x x x WAIT x x x x CONFIG 1 A x Slave to Master Set NV Mode CONFIG 0 S Chip ID + W A x Master to slave CONFIG 0 NV x A x x WAIT A x WAIT A ... WAIT A P Programming Time Chip ID + W 1 1 0 0 0 0 0 0 a R/W x x 7-Bit Address CONFIG 1 1 NV / V 0 0 NV Memory Address 0 x x Master to slave Slave to Master Set NV Mode CONFIG 0 x x x x WAIT x x x x NV x x x x The logic diagram above is for writing new CDAC data into memory, not an erase operation. 16 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 3.6.4 Read Operation With a valid device address and the R/W bit set to 1, the device will execute a Read Operation. Following the device address byte from the Master, the NCD2400M slave will output 4 bytes on the SDA bus: BYTE 3 will be output first; followed by BYTE 2; then BYTE 1; and last BYTE 0. • BYTE 3: bits = 0x8; bit is nv/v, the current Operating Mode (1 = Non-Volatile), (0 = Volatile); bits Address of last written Non-Volatile nibble; and bit is vr, the Volatile Register MSB • BYTE 2: bits are vr, the Volatile Register bits • BYTE 1: bits = 0x0; bit is “a”, the I2C Chip ID address LSB; bits = 0x2; and bit is nv, the Non-Volatile memory MSB • BYTE 0: bits are nv, the Non-Volatile memory bits . A read command instructs the NCD2400M to perform two tasks. Data in Non-Volatile Memory is passed to the CDAC non-volatile controller register which configures the programmable capacitor when operating in the Non-Volatile Mode. And second, the NCD2400M will output its stored contents onto the SDA bus as described above. The content output onto the bus of the Volatile Register and the Non-Volatile Memory is the last data written into these locations. Reading the device after a power up reset and before a write to the Volatile Register will return a value of 0x000 for the contents of the Volatile Register. This is because the Volatile Register is cleared at power up. When the device is returned to the Non-Volatile Mode by means of the “Set Non-Volatile Mode” command, a read operation will return the last value written into the Volatile Register. Data format of a read operation is illustrated in the diagram below READ OPERATION. S Chip ID + R A Chip ID + R 1 BYTE 3 1 0 A BYTE 2 0 0 A BYTE 1 0 0 1 a R/W NV_Addr VR 1 NV 7-Bit Address BYTE 3 1 0 0 0 BYTE 2 BYTE 1 BYTE 0 R01 NV/V A BYTE 0 A P Master to slave Slave to Master VR 0 0 0 0 a 0 NV www.ixysic.com 17 NCD2400M INTEGRATED CIRCUITS DIVISION 3.6.5 Set Non-Volatile Mode Operation A valid Device Address with the R/W bit set to 0, and CONFIG1 configured as shown below, the device will convert to the Non-Volatile Mode. Once this operation is executed, the NCD2400M will be operating in the Non-Volatile Mode and the output capacitance value will reflect the value stored in the Non-Volatile CDAC. A Read command or power up reset is required to pass any updated value stored in the Non-Volatile Memory to the Non-Volatile CDAC. The NCD2400M Set Non-Volatile command changes the operating mode from Volatile to Non-Volatile. This is accomplished by using a non-volatile write command. The command data structure uses only the upper nibble of CONFIG 1 by setting CONFIG 1 to 0x9. The upper nibble consists of: CONFIG 1, the NV/V control bit; CONFIG 1, the non-volatile memory address; and CONFIG 1, the Set Non-Volatile Mode control bit. The lower nibble bits, CONFIG 1, are Don’t Cares. This operation does not alter the contents of the Volatile Register. Therefore any Read command after the Set Non-Volatile Mode will reflect the last CDAC code written to the volatile register. A power up reset will clear the register contents. The data format for the Set Non-Volatile Mode command is shown in the diagram below Additionally, all of CONFIG 0 bits of the Set Non-Volatile command are Don’t Cares. SET NON-VOLATILE MODE OPERATION. S Chip ID + W A Chip ID + W 1 1 0 CONFIG 1 0 0 A 0 7-Bit Address CONFIG 1 1 NV / V CONFIG 0 18 x 0 0 NV Memory Address x x 1 CONFIG 0 A P 0 0 a R/W x x x x x x x x Master to Slave Slave to Master Set NV Mode x www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 3.6.6 Electrical and Timing Considerations The electrical and timing conditions that must be followed for reliable programming are provided in Section 1.8 "Digital Interface: Electrical Characteristics of SDA and SCL” and Section 1.9 "Digital Interface: AC Characteristics” on page 5 and are repeated below for convenience. For applications where there are no other devices on the bus and the capacitance loading of the interconnection traces is low, it may be possible to avoid using external pull-up resistors by using only the internal pull-up resistors. Internal pull up resistors at SDA and SCL with a nominal value of 135k maintain an inert logic '1' state at these inputs to ensure stable and predictable behavior without the need for supplementary external components for lightly loaded busses. This is especially useful for customers who want to do one time programming and do not need to adjust the capacitance value during normal operation. For these applications the pins may be left unterminated. SCL SDA VDD 135kΩ Configuring or programming the NCD2400M must be done under the following conditions: • Serial Clock: fSCL= 400kHz max. • Serial Clock: DSCL= 50% ± 10% • Non-Volatile programming, nominal duration tPNV = 5ms. 135kΩ MASTER NCD2400M Slave 0x60 VDD 135kΩ 135kΩ NCD2400M1 Slave 0x61 3.7 Capacitor Interface Electrical and Biasing Considerations 3.6.7 Application Diagrams The recommended application circuit for I2C communication between the Master and two NCD2400M devices operating as slaves, is shown in the diagram below. It is recommended to use properly valued pull-up resistors on both the SDA and SCL nets to accommodate any additional devices attached to the bus and loading due to the PCB interconnection traces. VDD VDD Proper biasing of the capacitor pins CP and CN is required to ensure analog performance of the NCD2400M. Because these pins are not self biased, it is necessary for the user to provide the required DC bias with sufficient headroom for the AC waveform thereby preventing signal distortion caused by clipping. Additionally the maximum signal level into these pins must not be exceeded. The voltage limitations for CP and CN are given in Section 1.4 "Recommended Operating Conditions” on page 3. SCL SDA VDD 135kΩ 135kΩ MASTER R01 NCD2400M Slave 0x60 VDD 135kΩ 135kΩ NCD2400M1 Slave 0x61 www.ixysic.com 19 NCD2400M INTEGRATED CIRCUITS DIVISION 4. Capacitance Determination and Programming Procedure Users who want to operate the NCD2400M in the Non-Volatile Mode upon power up will need to preprogram the appropriate CDAC code into memory. The two phases of this procedure are: Different sequences than the one described above, such as erasing all memory nibbles before writing new values to them, are permitted. • Capacitance Code Determination • Capacitance Code Programming Trimming the NCD2400M capacitance to the optimal value is best accomplished in the Volatile Mode. CDAC code changes to the Volatile Register require fewer I2C write operations and the capacitance value change is immediate, no need to perform a Read command to execute the code update. Once the code for the desired capacitance value is known, it needs to be stored in the Non-Volatile memory by means of the Non-Volatile write command. Three separate write commands are required to program all three nibble of the Non-Volatile memory. Before writing a new code into the Non-Volatile Memory it must be erased in order to delete any old content. The recommended procedure for this is given below. For a device with address 0x60, the sequence to write capacitance codes 0x125, 0x126, 0x127 and 0x128 to the Volatile Register and then programming 0x127 into the Non-Volatile Memory is as follows: All commands will be to device address 0x60. Write 0x125 into the Volatile Register. Write 0x126 into the Volatile Register. Write 0x127 into the Volatile Register. Write 0x128 into the Volatile Register. Write 0x127 into the Non-Volatile Memory using following sequence: • Erase memory nibble 0x0: Write 0x0 into non-volatile memory address 0x0 • Write 0x7 into non-volatile memory address 0x0 • Erase memory nibble 0x1: Write 0x0 into non-volatile memory address 0x1 • Write 0x2 into non-volatile memory address 0x1 • Erase memory nibble 0x2: Write 0x0 into non-volatile memory address 0x2 • Write 0x1 into non-volatile memory address 0x2 • Read the memory content using the Read command. • Set Non-Volatile mode. Note that the capacitance value won't change and will correspond to the content of the Volatile Register unless the mode is changed to Non-Volatile. • • • • • • 20 www.ixysic.com R01 NCD2400M INTEGRATED CIRCUITS DIVISION 5. Manufacturing Information 5.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Classification NCD2400M - All Versions MSL 1 5.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 5.3 Soldering Profile Provided in the table below is the Classification Temperature (TC) of this product and the maximum dwell time the body temperature of this device may be (TC - 5)ºC or greater. The classification temperature sets the Maximum Body Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other processes, the guidelines of J-STD-020 must be observed. Device Classification Temperature (TC) Dwell Time (tp) Max Reflow Cycles NCD2400M - All Versions 260°C 30 seconds 3 5.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based. R01 www.ixysic.com 21 NCD2400M INTEGRATED CIRCUITS DIVISION 5.5 Mechanical Dimensions 5.5.1 Package Dimensions 2.000±0.050 (0.079±0.002) Recommended PCB Land Pattern 0.750±0.050 (0.030±0.002) 0.203 REF (0.008 REF) Pin 1 2.000±0.050 (0.079±0.002) 1.300 REF (0.051 REF) 2.10 (0.083) 0.35 (0.014) 0.025±0.025 (0.001±0.001) 0.650 BSC (0.026 BSC) 0.65 (0.026) 0.65 (0.026) 1.000±0.050 (0.039±0.002) Dimensions mm (inches) 1.600±0.050 (0.063±0.002) Pin 1 ID 0.300±0.050 (0.012±0.002) Chamfer 0.300 x 45º Note: Dimensions do not include mold or interlead flash, protrusions or gate burrs. 0.250±0.050 (0.010±0.002) 5.5.2 Tape & Reel Specification 2.00±0.05 (0.079±0.002) 4.00±0.10 (0.157±0.004) 1.75±0.10 (0.069±0.004) 177.8 DIA. (7.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) 2.30±0.05 (0.091±0.002) A ∅ 1.50 +0.1 -0 8.00 +0.30 -0.10 (∅ 0.059 +0.004 -0) (0.315 +0.012 -0.004) A 3.50±0.05 (0.138±0.002) Pin 1 4.00 (0.157) 1.00±0.05 (0.039±0.002) User direction of feed 2.30±0.05 (0.091±0.002) Embossed Carrier Section A-A Embossment NOTE: Devices oriented in tape as shown. ∅ 1.00 +0.25 (∅ 0.039 +0.010) Dimensions mm (inches) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-NCD2400M-R01 © Copyright 2018, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 4/!3/2018 22 www.ixysic.com R01