KIC7SZ38FU

SEMICONDUCT OR TECHNICAL DATA 2 INPUT NAND GATE (Open Drain Output) FEATURES ・Open Drain Output Stage for OR tied application. ・Super High Speed : 2.4ns(Typ.) 50pF at VCC=5V. ・High Output Sink Drive : 24mA at VCC=3V. ・Operating Voltage Range : VCC(opr)=1.65~5.5V. ・Power Down High Impedance Inputs/Outputs. A1 A KIC7SZ38FU SILICON MONOLITHIC CMOS DIGITAL INTEGRATED CIRCUIT B B1 1 5 2 3 4 D H T G DIM A A1 B B1 C D G H T MILLIMETERS _ 2.00 + 0.20 _ 1.3 + 0.1 _ 2.1 + 0.1 _ 1.25 + 0.1 0.65 0.2+0.10/-0.05 0-0.1 _ 0.9 + 0.1 0.15+0.1/-0.05 MAXIMUM RATINGS (Ta=25℃) CHARACTERISTIC Power Supply Voltage Range DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC/Ground Current Power Dissipation Storage Temperature Range Lead Temperature (10s) SYMBOL VCC VIN VOUT IIK IOK IOUT ICC PD Tstg TL RATING -0.5~6 -0.5~6 -0.5~6 -50~20 -50~20 50 ±50 200 -65～150 260 UNIT V V V mA mA mA mA mW ℃ ℃ C C USV MARKING Type Name TN PIN CONNECTION(TOP VIEW) IN B 1 5 VCC IN A 2 GND 3 4 OUT Y 2002. 5. 13 Revision No : 0 1/3 KIC7SZ38FU Logic Diagram (1) (2) IN B IN A & (4) OUT Y ELECTRICAL CHARACTERISTICS DC Characteristics CHARACTERISTIC SYMBOL TEST CONDITION VCC(V) 1.65~1.95 MIN. 0.75× VCC Ta=25℃ TYP. 0 0 0 0 0 0.08 0.10 0.15 0.22 0.22 MAX. 0.25× VCC 0.3×VCC ±5 0.1 0.1 0.1 0.1 0.1 0.24 0.3 0.4 0.55 0.55 ±1 1 2.0 Ta=-40~85℃ MIN. 0.75× VCC 0.7×VCC MAX. 0.25× VCC 0.3×VCC ±10 0.1 0.1 0.1 0.1 0.1 0.24 0.3 0.4 0.55 0.55 ±10 10 20 μ A μ A μ A V μ A V UNIT High Level Input Voltage Low Level VIH 2.3~5.5 0.7×VCC VIL VIN=VIL VOUT = VCC or GND 1.65~1.95 2.3~5.5 High Level ILKG 5.5 1.65 1.8 IOL=100μ A 2.3 3.0 Low Level VOL VIN=VIH 4.5 IOL=4mA IOL=8mA IOL=16mA IOL=24mA IOL=32mA 1.65 2.3 3.0 3.0 4.5 0~5.5 0.0 5.5 - Output Leakage Voltage Input Leakage Current Power Off Leakage Current Quiescent Supply Current IIN IOFF ICC VIN=5.5V or GND VIN or VOUT=5.5V VIN=5.5V or GND 2002. 5. 13 Revision No : 0 2/3 KIC7SZ38FU AC Characteristics (unless otherwise specified, Input : tr=tf=3ns) CHARACTERISTIC SYMBOL TEST CONDITION VCC(V) CL=50pF, RU=500Ω RD=500Ω VI=2×VCC (Figures 1,3) CL=50pF, RU=500Ω RD=500Ω VI=2×VCC (Figures 1,3) (Note) (Figures 2) 1.65 1.8 2.5±0.2 3.3±0.3 5.0±0.5 1.65 1.8 2.5±0.2 3.3±0.3 5.0±0.5 0 0 3.3 5.0 MIN. 1.5 1.5 0.8 0.8 0.5 1.5 1.5 0.8 0.8 0.5 Ta=25℃ TYP. 6.5 5.4 3.5 2.8 2.2 5.5 4.6 3.0 2.1 1.3 4 5 5.1 7.3 MAX. 12.7 10.5 7.0 5.0 4.3 12.7 10.5 7.0 5.0 4.3 Ta=-40~85℃ MIN. 1.5 1.5 0.8 0.8 0.5 1.5 1.5 0.8 0.8 0.5 MAX. 13.2 11.0 7.5 5.2 4.5 13.2 11.0 7.5 5.2 4.5 pF pF pF ns ns UNIT tPZL Propagation delay time tPLZ Input Capacitance Output Capacitance Power Dissipation Capacitance CIN COUT CPD Note : CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure2.) CPD is related to ICCD dynamic operating current by the expression : ICCD=CPD・VCC・fIN+ICC Static AC Loading and Waveforms VCC VCC A OUTPUT INPUT CL RD RU INPUT CL includes load and stray capacitance Input PRR=1.0MHz ; t w =500ns Input=AC Waveform ; t r =tf =1.8ns PRR=10MHz ; Duty Cycle=50% FIGURE 1. AC Test Circuit FIGURE 2. ICCD Test Circuit t r =3ns t f =3ns 90% 50% 10% t PLZ VOH VCC INPUT tw t PZL GND OUTPUT 50% VOL +0.3V VOL FIGURE 3. AC Waveforms 2002. 5. 13 Revision No : 0 3/3