KUSB50QN

SEMICONDUCTOR TECHNICAL DATA HIGH-SPEED(480Mbps) USB2.0 DPDT SWITCH DESCRIPTION The KUSB50QN is a High-Speed(480Mbps) USB2.0 signal switch. Configured as a double-pole double-throw (DPDT) switch, it is optimized for switching between 2 Hi-Speed sources or a Hi-Speed(480Mbps) and Full-Speed(12Mbps) source. Its wide Bandwidth (720MHz) is wide enough to pass High-Speed USB2.0 differential signals. Industry-leading advantages include a propagation delay of less than 250ps, resulting from its low channel resistance and low on capacitance. It is bidirectional and offers little or no attenuation of the High-Speed signal at the outputs. Its high channel-to-channel crosstalk rejection results in minimal noise interference. The switch is designed to minimize current consumption even when the control voltage applied to the S pin, is lower than the VCC. The KUSB50QN also offers over-voltage protection per the USB2.0 Specification. With the chip powered ON or OFF, all data I/O pins can withstand a short to Vbus(5.25V). FEATURES ・USB2.0 compliant (High-speed and Full-speed). ・Low On Resistance, 5.5Ω(Typ) @ VCC=3V . ・Channel On Capacitance, 6.5㎊(Typ) @ f=1㎒. ・Low Power Consumption (Max :1㎂) : 10㎂Maximum ICCT over an Expanded Voltage Range (VIN=1.8V, VCC=4.3V). ・Wide-3dB bandwidth, >720MHz. ・High ESD Protection. :Data Pin ESD Rating : 8.0kV(HBM) Control Pin ESD Rating : 8.0kV(HBM) Power/GND ESD Rating : > 20kV(HBM) All pins ESD Rating : 300V(MM). ・Power Off protection : When VCC =0V, D+/D -can tolerate up to 5.25V B Pin 1 KUSB50QN HIGH-SPEED USB2.0 DPDT SWITCH F E CO.1 G D A TOP VIEW H C BOTTOM VIEW J SIDE VIEW 1 I SIDE VIEW 2 K DIM A B C D E F G H I J K MILLIMETERS _ 1.80 + 0.05 _ 1.40 + 0.05 _ 0.20 + 0.05 _ 0.40 + 0.10 0.20 REF 0.40 REF 0.80 REF _ 0.50 + 0.10 0.05 Max 0.20 REF _ 0.85 + 0.05 QFN-10 Marking U2 0A APPLICATIONS ・Routes signals for USB2.0 ・Differential Signal Data Routing ・Hand-held devices 2010. 2. 10 Revision No : 0 1/10 KUSB50QN Pin Configuration Block Diagram HSD1+ HSD1- HSD1+ D+ 5 4 HSD2+ HSD2GND OE VCC S 8 9 10 7 6 HSD2+ 1 D+ 2 D- 3 HSD1DHSD2- Top View S OE Control Truth Table S X HIGH LOW OE HIGH LOW LOW Diretion Disconnect D+, D- = HSD1x D+, D- = HSD2x Pin Descriptions PIN 1 2 3 4 5 6 7 8 9 10 HSD2HSD2+ HSDnx HSD1HSD1+ OE (OE-) VCC S Data Port Data Port Bus Switch Enable Control Supply Voltage Select Input Control D+ Dx DGND Data Port Ground Data Port Data Port NAME Data Port Function 2010. 2. 10 Revision No : 0 2/10 KUSB50QN Absolute Maximum Ratings CHARACTERISTIC Supply Voltage Control Port Input Voltage (S, OE-) Switch Input Voltage (HSDnx, Dx) Data Port Output Current Power Dissipation Operating Ambient Temperature Storage Temperature Range SYMBOL VCC VIN HSDnx VSW Dx @VCC>0 Dx @VCC=0 IOD PD Ta Tstg 120 0.5 -40 ~ +85 -65 ~ +150 RATING -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 5.25 mA W ℃ ℃ V UNIT V V DC Electrical Characteristics⑴ (VCC=3.0~4.3V, Ta = -40~85℃) PARAMETER Input HIGH Voltage SYMBOL VIH TEST CONDITIONS VCC=4.3V VCC=3.0V VCC=4.3V VCC=3.0V VCC=Max, IIN=-18mA VCC=Max, 0≤VIN≤VCC VCC=VOE-=Max, 0≤VSW≤VCC VCC=0V, 0≤VSW≤4.3V VCC=Max, VIN=0V or VCC VCC=Max, VIN=1.8V VCC=Min, 0V≤VSW≤1.0V, ION=-40mA VCC=Min, 0V≤VSW≤1.0V, ION=-40mA VCC=Min, VSW=1.0V, ION=-40mA MIN 1.7 1.3 -1.0 -2.0 -2.0 TYP -0.7 5.5 1.5 0.2 MAX 0.7 0.5 -1.2 1.0 2.0 2.0 1.0 10.0 6.5 0.35 UNITS V V V V V μ A μ A μ A μ A μ A Ω Ω Ω Input LOW Voltage Clamp Diode Voltage Control Input Leakage OFF State Leakage Power OFF Leakage Current (D+, D-) Quiescent Supply Current Increase in ICC per Control Voltage Switch ON Resistance ON Resistance Flatness ON Resistance Match from Center Port to any other port VIL VIK IIN IOZ IOFF ICC ICCT RON RFLAT(ON) ΔRON Note(1) : All typical values are at VCC=3.3V(unless otherwise noted), Ta=25℃ Capacitance Characteristics⑴ (Ta =-40~85℃, f=1㎒) PARAMETER HSDnx, Dnx, Switch ON Capacitance HSDnx, Switch OFF Capacitance Control Pin Input Capacitance SYMBOL CON COFF CIN TEST CONDITIONS VCC=3.3V, VOE-=0V VCC=3.3V, VOE-=3.3V VCC=0V MIN TYP 6.5 3.0 3.6 MAX UNITS FIGURE NO. pF pF pF 6 7 7 2010. 2. 10 Revision No : 0 3/10 KUSB50QN AC Electrical Characteristics⑴ (Ta = -40~85℃) PARAMETER Propagation Delay(2) Turn-On Time Turn-Off Time Break-Before-Make -3dB Bandwidth Off Isolation (Non-Adjacent) Channel Crosstalk (Non-Adjacent) SYMBOL tPD tON tOFF tBBM BW OIRR XTALK TEST CONDITIONS VCC=3.3V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, RT=50Ω 3.0≤VCC≤3.6V, RT=50Ω, f=240㎒ 3.0≤VCC≤3.6V, RT=50Ω, f=240㎒ CL=0pF CL=5pF MIN 2.0 TYP 0.25 13.0 12.0 720 550 -30.0 -45.0 MAX 30.0 25.0 6.5 UNITS FIGURE NO. ns ns 10 ns ns ㎒ dB dB 11 13 14 15 9 Note(2) : Guaranteed by characterization. AC Electrical Characteristics For USB2.0 High-Speed Switching ⑴ (Ta = -40~85℃) PARAMETER Skew of Opposite Transitions of the Same Output(2) Channel-to-Channel Skew(2) Total Jitter(2) SYMBOL tSK(P) tSK(O) tJ(2) TEST CONDITIONS 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF tR=tF=500ps at 480Mbps MIN TYP 20 50 200 MAX UNITS FIGURE NO. ps 12 ps ps - 2010. 2. 10 Revision No : 0 4/10 KUSB50QN Application Information VCC USB2.0 Controller Set Top Box (STB) CPU or DSP Processor DVR or Mass Storage Controller HSD1+ KUSB50QN D+ HSD1- USB Connector D- HSD2+ HSD2S Control OE Fig. 1 Application Diagram 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 Differential Signal (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time ( x 10-9)(s) Measurement Name Eye Diagram Test Signal Rate (Mbps) EOP Width (Bits) Rise Time (ns) Fall Time (ns) Consecutive Jitter Range KJ Paired Jitter Range JK Paired Jitter Range 788.3502 798.1337 Minimum 442.4563 Maximum 527.4987 2.399811 2.396142 Mean 480.0518 16.56572 1.222390 1.214730 RMS 481.5582 1.304253 1.287723 STATUS PASS PASS PASS PASS PASS PASS PASS PASS -157.9ps to 139.6ps RMS Jitter 59.29ps -135.6ps to 138.3ps RMS Jitter 53.00ps -110.1ps to 155.5ps RMS Jitter 49.48ps Fig. 2 High-Speed Eye Diagram 2010. 2. 10 Revision No : 0 5/10 KUSB50QN 4.0 3.5 3.0 Differential Signal (V) 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Time ( x 10-8)(s) Measurement Name Eye Diagram Test Signal Rate (Mbps) Crossover Voltage EOP Width (Bits) Rise Time (ns) Fall Time (ns) Consecutive Jitter Range KJ Paired Jitter Range JK Paired Jitter Range Minimum 11.98705 1.622501 Maximum 12.02102 1.735276 - Mean 12.00205 1.678898 167.017 7.3464 7.4212 RMS 12.00283 7.3472 7.4230 STATUS PASS PASS PASS PASS PASS PASS PASS PASS PASS 7.2297 7.1852 7.5460 7.6988 -188.3988ps to 140.1242ps RMS Jitter 91.71091ps -178.1923ps to 110.7530ps RMS Jitter 137.6440ps -116.2675ps to 86.31155ps RMS Jitter 78.24693ps Fig. 3 Full-Speed Eye Diagram 2010. 2. 10 Revision No : 0 6/10 KUSB50QN Test Diagram (Continued) VCC HSDn VIN GND KUSB50QN D VOUT RON = VON / ION ION VON = VIN -VOUT VS = VIL or VIH S VS GND GND Fig. 4 Switch On Resistance VCC KUSB50QN NC D IOZ or IOFF A VIN IOFF = (VCC = 0V) IOZ (VOE- =VCC) VS = VIL or VIH Each Data Ports is tested separately S OEGND VS VOE- GND Fig. 5 OFF Leakage VCC VCC KUSB50QN D Capacitance Meter Freq=1MHz HSDn S VS = 0V or VCC Capacitance Meter Freq=1MHz VS = 0V or VCC S D KUSB50QN HSDn GND GND Fig. 6 Channel On Capacitance Fig. 7 Channel OFF Capacitance 2010. 2. 10 Revision No : 0 7/10 KUSB50QN VCC KUSB50QN HSD1 or 2 VIN GND HSD2 or 1 S OEVOECL RL D+, DVOUT 1. RL and CL are functions of application environment. 2. CL includes test jig and probe capacitance. VS GND GND GND GND Fig. 8 AC Test Circuit tRISE=500ps 800mV Input : HSDn 400mV 10% 90% 50% 90% 50% tFALL=500ps 10% VOH Output : D 50% 50% VOL tPLH tPHL Fig. 9 Propagation Delay Time tRISE=2.5ns VCC Input : S, OEGND 10% 90% 90% tFALL=2.5ns VCC/2 VCC/2 10% VOH Output : D 90% 90% VOL tON tOFF Fig. 10 Turn-On / Turn-Off Time 2010. 2. 10 Revision No : 0 8/10 KUSB50QN VCC KUSB50QN HSD1 or 2 VIN GND S Control Input HSD2 or 1 VCC VOUT RL CL* Control Input D+, D- 50% 0V tR=tF=2.5ns (10-90%) GND GND GND VOUT 0.9 VOUT GND tD *CL includes test jig and probe capacitance. Fig. 11 Break-Before-Make tRISE=500ps 800mV Input : D 90% 50% 10% 90% 50% tFALL=500ps tRISE=500ps 800mV Input : HSDn 400mV 10% 90% 50% 90% 50% tFALL=500ps 400mV 10% VOH Output1 : HSD1 10% 50% 50% VOL VOH tPLH1 tPHL1 VOH Output : D 50% 50% Output2 : HSD2 50% 50% VOL tPLH TSK(P) = tPHL - tPLH Pulse Skew, TSK(P) tPHL VOL tPLH2 TSK(O) = tPHL1 - tPLH2 or tPHL1 - tPLH2 tPHL2 Output Skew, TSK(OUT) Fig. 12 Skew Tests 2010. 2. 10 Revision No : 0 9/10 KUSB50QN VCC Network Analyzer D GND VIN RS Signal Source KUSB50QN VS GND HSDn GND RT GND VOUT GND BW = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 13 Bandwidth VCC Network Analyzer D RT GND VIN RS Signal Source KUSB50QN VS GND GND HSDn GND VOUT RT GND GND GND OIRR = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 14 Channel OFF Isolation VCC Network Analyzer D-(NC) D+ HSD1+ (HSD2+) RT GND VIN RS Signal Source KUSB50QN VS GND GND GND GND HSD1(HSD2-) GND RT GND VOUT XTALK = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 15 Non-adjacent Channel-to-Channel Crosstalk 2010. 2. 10 Revision No : 0 10/10