KK4017BN

TECHNICAL DATA Counter/Divider The KK4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply KK4017B N S UFFIX PL AST IC 16 1 16 1 DW SU FFIX S O IC ORDERING INFORMATION KK4017BN Plastic KK4017BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Clock L X X Clock Enable X H X Reset L L H Output State no change no change reset counter Q0=H, Q1-Q9=L, C0=H Advance to next state no change no change Advance to next state L X X PIN 16 =VCC PIN 8 = GND H L L L L Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X=don’t care 1 KK4017B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP** SOIC Package** Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to 20 -0.5 to VCC 0.5 -0.5 to VCC 0.5 ±10 750 500 100 -65 to 150 260 Unit V V V mA mW mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC 125 Unit V V °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK4017B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit ≥-55°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 ±0.1 1.0 2.0 4.0 20 0.64 1.6 4.2 -0.64 –2.0 –1.8 –4.2 2 5 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 ±0.1 1.0 2.0 4.0 20 0.51 1.3 3.4 -0.51 –1.6 –1.3 –3.4 ≤125 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 ±1.0 30 60 120 600 0.36 0.9 2.4 mA -0.36 –1.15 –0.9 –2.4 Unit V VIL V VOH V VIL=1.5V, VIH=3.5V, IO=-1µA VIL=3.0V, VIH=7.0V, IO=-1µA VIL=4.0V, VIH=11V, IO=-1µA VOL Maximum Low-Level Output Voltage VIN=GND or VCC V VIL=1.5V, VIH=3.5V, IO=1µA VIL=3.0V, VIH=7.0V, IO=1µA VIL=4.0V, VIH=11V, IO=1µA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current VIN= GND or VCC VIN= GND or VCC µA µA IOL VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V mA IOH Minimum Output VIN= GND or VCC High (Source) Current VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V 3 KK4017B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input tr=tf=20 ns) VCC Symbol fmax Parameter Maximum Clock Frequency V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 Guaranteed Limit ≥-55°C 2 5 °C 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 5 ≤125°C 2.0 4.0 5.0 800 350 250 750 300 200 300 150 120 700 300 250 Unit MHz tPLH, tPHL Maximum Propagation Delay, Clock to Decode Output (Figure 1) Maximum Propagation Delay, Clock to Carry Output (Figure 1) Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) Maximum Propagation Delay, Reset to Carry Output or Decode Output (Figure 1) Maximum Input Capacitance ns tPLH, tPHL ns tTLH, tTHL ns tPLH, tPHL ns CIN pF TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF, Input tr=tf=20 ns, RL=200kΩ ) VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 260 110 60 400 280 150 230 100 70 200 90 60 Guaranteed Limit ≥-55°C 2 5 °C 200 90 60 UNLIMITED 260 110 60 400 280 150 230 100 70 400 180 100 550 400 200 300 150 100 ≤125°C 300 150 100 Unit ns tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 1) µs tw ns trem Minimum Removal Time, Reset (Figure 1) ns tSU Minimum Setup Time, Clock Inhibit to Clock (Figure 1) ns 4 KK4017B t su 50% CLOCK CLOCK INHIBIT 50% 90% 90% 50% 50% 10% 10% 1/f max 50% 50% tw VCC 50% tf tr GND t rem VCC GND tw VCC 50% 50% RESET t PLH DECODE Q1-Q9 OUTPUT 50% t PHL 50% GND VCC GND t PLH 90% 10% 50% t PHL DECODE Q0 OR 90% CARRY OUTPUT 10% 50% VCC GND t Figure 1. Switching Waveforms Timing diagram 5 KK4017B EXPANDED LOGIC DIAGRAM 6 KK4017B N SUFFIX PLASTIC (MS - 001BB) A 16 9 B 1 8 Dimensions, mm Symbol A B MIN 18.67 6.10 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.20 0.38 10° 3.81 8.26 0.36 MAX 19.69 7.11 5.33 0.56 1.78 F L C D F C -T- SEATING PLAN E N G D 0.25 (0.010) M T K M H J G H J K L M N NOTES: 1. imensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AC) A 16 9 Dimensions, mm Symbol. MIN 9.80 3.80 1.35 0.33 0.40 1.27 5.72 0° 0.10 0.19 5.80 0.25 8° 0.25 0.25 6.20 0.50 MAX 10.0 4.00 1.75 0.51 1.27 B P H A B C C R x 45 1 G 8 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE J F M H J K M P R NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for B - 0.25 mm (0.010) per side. 7