KK4502BD

TECHNICAL DATA KK4502B Strobed Hex Inverter/Buffer High-Voltage Silicon-Gate CMOS The KK4502B consists of six inverter/buffers with 3-state outputs. A logic “1” on the OUTPUT ENABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A logic “1” on the DIRECTION input switches all six outputs to logic “0” if the OUTPUT ENABLE input is a logic “0”. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION KK4502BN Plastic KK4502BD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Output Enable L L L H PIN 16=VCC PIN 8= GND Direction L L H X A L H X X Output Y H L L Z Z = high impedance X = don’t care 1 KK4502B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V mA mW mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK4502B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=0.5 V VOUT=1 V VOUT=1.5 VOUT= VCC - 0.5V VOUT= VCC - 1.0 V VOUT= VCC - 1.5V VIN=GND V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 18 Guaranteed Limit ≥-55°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 1 2 4 20 3.84 9.6 25.2 -2 -0.64 -1.6 -4.2 ±0.4 2 5 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 1 2 4 20 3.06 7.8 20.4 -1.6 -0.51 -1.3 -3.4 ±0.4 ≤125 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±1.0 30 60 120 600 2.16 5.4 14.4 mA -1.15 -0.36 -0.9 -2.4 ±12 µA Unit V VIL V VOH V VOL VIN= VCC V IIN ICC VIN= GND or VCC VIN= GND or VCC µA µA IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V Maximum Tree-State Leakage Current Output in High-Impedance State VIN= GND or VCC VOUT= GND or VCC IOZ 3 KK4502B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ unless otherwise specified, Input tr=tf=20 ns) VCC Symbol tPHL Parameter Maximum Propagation Delay, Input A or Direction to Output Y (Figure 1) Maximum Propagation Delay, Input A or Direction to Output Y (Figure 1) Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ Maximum Output Transition Time, Any Output (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance Maximum Tree-State Output Capacitance (Output in High-Impedance State) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 270 120 80 380 180 130 120 80 60 220 100 80 250 130 110 250 110 80 200 100 80 120 60 40 Guaranteed Limit ≥-55°C 2 5 °C 270 120 80 380 180 130 120 80 60 220 100 80 250 130 110 250 110 80 200 100 80 120 60 40 7.5 15 ≤125°C 540 240 160 760 360 260 240 160 120 440 200 160 500 260 220 500 220 160 400 200 160 240 120 80 Unit ns tPLH ns tPHZ ns tPZH ns tPLZ ns tPZL ns tTLH ns tTHL ns CIN COUT pF pF 4 KK4502B Figure 1. Switching Waveforms Figure 2. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/6 of the Device) 5 KK4502B N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6