KK7406

TECHNICAL DATA KK7406 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs The KK7406 monolithic TTL hex inverter buffers/drivers feature high-voltage open collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and are also characterized for use as inverter buffers for driving TTL inputs. • • • • • Minimum breakdown Voltages is 30 V Maximum sink Current is 40 mА Converts TTL Voltage Levels to MOS Levels Open-Collector Driver for Indicator Lamps and Relays Inputs Fully Compatible with MOST TTL Circuits. ORDERING INFORMATION KK7406N Plastic KK7406D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs A L H Z = High Impedance Output Y Z L Y=Ā PIN 14 =VCC PIN 7 = GND 1 KK7406 MAXIMUM RATINGS* Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 5.5 30 -65 to +150 Unit V V V °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL UOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Current Ambient Temperature Range -10 Parameter Min 4.75 2.0 0.8 30 40 +70 Max 5.25 Unit V V V V mA °C DC ELECTRICAL CHARACTERISTICS Guaranteed Limit Symbol VIK IOH VOL IIH IIL ICC Parameter Input Clamp Voltage High Level Output Current Low Level Output Voltage High Level Input Current Low Level Input Current Supply Current Test Conditions VCC = 4.75V, IIN = -12 mA VCC = 4.75V, VOH =30V VCC = 4.75V, IOL = 16 mA VCC = 4.75V, IOL = 40 mA VCC = 5.25V, VIN = 2.4 V VCC = 5.25V, VIN = 0.4 V VCC = 5.25V Outputs High Outputs Low Min Max -1.5 0.25 0.4 0.7 0.04 -1.6 48 51 mA mA mA Unit V mA V 2 KK7406 AC ELECTRICAL CHARACTERISTICS (T = 25°C, VCC = 5.0 V, CL = 15 pF, RL = 110 Ω, Input tr = tf = 10 ns) Symbol tPLH tPHL Parameter Propagation Delay Time, Low to High Level Output (from Input to Output) Propagation Delay Time, High to Low Level Output (from Input to Output) Min Max 18 28 Unit ns ns Figure 1. Switching Waveforms * Includes all probe and jig capacitance Figure 2. Test Circuit 3 KK7406 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 4