KK74180

TECHNICAL DATA KK74180 9-Bit ODD/EVEN Parity Generators/Checkers LOGIC DIAGRAM ORDERING INFORMATION KK74180N Plastic KK74180D SOIC TA = -10° to 70° C for all packages PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND FUNCTION TABLE Inputs Σ of H’s at EVEN A Thru H EVEN ODD EVEN ODD X X X =don’t care H H L L H L ODD L L H H H L Output Σ EVEN H L L H L H Σ ODD L H H L L H 1 KK74180 MAXIMUM RATINGS* Symbol VCC VIN IOL Tstg * Parameter Supply Voltage Input Voltage Low Level Output Current Storage Temperature Range Value 7.0 5.5 16 -65 to +150 Unit V V mA °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Ambient Temperature Range -10 Parameter Min 4.75 2.0 0.8 -800 16 +70 Max 5.25 Unit V V V µA mA °C DC ELECTRICAL CHARACTERISTICS over full operating conditions Symbol VIK VOH VOL II Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current at Maximum Input Voltage High Level IIH Input Current Low Level IIL IOS* ICC Input Current Supply Current Any data input Even or odd input Any data input Even or odd input VCC = max, VIN = 0.4 V VCC = max VCC = max, See Note -18 VCC = max, VIN = 2.4 V Test Conditions VCC = min, IIN = -10 mA VCC = min, IOH=max VCC = min, IOL=max VCC = max, VIN= 5.5 V 2.4 0.4 1 40 80 -1.6 -3.2 -55 56 mA mA mA µA Guaranteed Limit Min Max -1.5 V V V mA Unit Short-Circuit Output Current *Not more than one output should be shorted at a time. Note: ICC is measured with even and odd inputs at 4.5 V, all other inputs and outputs open. 2 KK74180 AC ELECTRICAL CHARACTERISTICS (T = 25°C, VCC = 5.0 V, CL = 15 pF, RL = 390 Ω, Input tr = tf = 10 ns) Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH Parameter Propagation Delay Time, Low to High Level Output (from Data toΣ EVEN) Propagation Delay Time, High to Low Level Output (from Data toΣ EVEN) Propagation Delay Time, Low to High Level Output (from Data toΣ ODD) Propagation Delay Time, High to Low Level Output (from Data toΣ ODD) Propagation Delay Time, Low to High Level Output (from Data toΣ EVEN) Propagation Delay Time, High to Low Level Output (from Data toΣ EVEN) Propagation Delay Time, Low to High Level Output (from Data toΣ ODD) Propagation Delay Time, High to Low Level Output (from Data toΣ ODD) Propagation Delay Time, Low to High Level Output (from EVEN or ODD to Σ EVEN or Σ ODD) Propagation Delay Time, High to Low Level Output (from EVEN or ODD to Σ EVEN or Σ ODD) EVEN input grounded 60 ns 68 20 ns ODD input grounded 48 ns 38 48 ns 38 Test Conditions Min Max 60 ns 68 Unit tPHL 10 Figure 1. Switching Waveforms Figure 2. Switching Waveforms NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 3. Test Circuit 3 KK74180 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 4