KK74AC163N

TECHNICAL DATA Presettable Counters High-Speed Silicon-Gate CMOS The KK74AC163 is identical in pinout to the LS/ALS163, HC/HCT163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The KK74AC163 is programmable 4-bit synchronous modulo-16 counter that feature parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The KK74AC163 is binary counter with synchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA; 0.1 µA @ 25° C • High Noise Immunity Characteristic of CMOS Devices • Outputs Source/Sink 24 mA KK74AC163 ORDERING INFORMATION KK74AC163N Plastic KK74AC163D SOIC TA = -40° to 85° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND Inputs Reset L H H H H X Load X L H H H X Enable P X X X L H X FUNCTION TABLE Outputs Enable T X X L X H X Clock Q0 L P0 Q1 L P1 Q2 L P2 Q3 L P3 Function Reset to “0” Preset Data No count No count Count No count No change No change Count up No change X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 1 KK74AC163 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74AC163 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 5.5 5.5 8.0 Guaranteed Limits 2 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 -40°C to 8 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 -75 80 µA mA mA µA V Unit V VIL VOUT= VCC-0.1 V V VOH IOUT ≤ -50 µA V VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT ≤ 50 µA * VIN=VIH IOL=12 mA IOL=24 mA IOL=24 mA IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND * * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC 3 KK74AC163 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol Parameter V Guaranteed Limits 2 5 °C Min fmax tPLH tPHL tPLH tPHL tPLH tPHL CIN Maximum Clock Frequency (Figure 1) Propagation Delay Clock to Q (Figure 1) Propagation Delay Clock to Q (Figure 1) Propagation Delay, Clock to Ripple Cary Out (Figure 1) Propagation Delay, Clock to Ripple Cary Out (Figure 1) Propagation Delay, Enable T to Ripple Carry Out (Figure 2) Propagation Delay, Enable T to Ripple Carry Out (Figure 2) Maximum Input Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 70 110 2.0 1.5 1.5 1.5 3.0 2.0 3.5 2.0 2.0 1.5 2.5 2.0 4.5 12.0 9.0 12.5 9.5 15.0 10.5 14.0 11.0 9.5 6.5 11.0 8.5 Max -40°C to 8 5 °C Min 60 95 1.5 1.0 1.5 1.5 2.5 1.5 2.5 2.0 1.5 1.0 2.0 1.5 4.5 13.5 9.5 13.0 10.0 16.5 11.5 15.5 11.5 11.0 7.5 12.5 9.5 Max MHz ns ns ns ns ns ns pF Unit Typical @25°C,VCC=5.0 V CPD * Power Dissipation Capacitance 45 pF Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V 4 KK74AC163 TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns) VCC Symbol tsu th tSU th tsu th tsu th tw tw Parameter Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) Minimum Hold Time, Clock to Preset Data Inputs (Figure 4) Minimum Setup Time, Reset to Clock (Figure 3) Minimum Hold Time, Clock to Reset (Figure 3) Minimum Setup Time, Load to Clock (Figure 5) Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 5) Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) Minimum Pulse Width, (Load) (Figure 3) Minimum Pulse Width, (Count) (Figure 3) V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Guaranteed Limit +25° C 13.5 8.5 -1.0 0 14 9.5 -1.0 -0.5 11.5 7.5 -1.0 -0.5 6.0 4.5 0 0 3.5 2.5 4.0 3.0 -4 0 ° C to +85° C 16.0 10.5 -0.5 0 16.5 11.0 -0.5 0 14.0 8.5 -0.5 0 7.0 5.0 0 0.5 4.0 3.0 4.5 3.5 Unit ns ns ns ns ns ns ns ns ns ns 5 KK74AC163 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform Figure 5. Switching Waveform 6 KK74AC163 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram 7 KK74AC163 EXPANDED LOGIC DIAGRAM 8 KK74AC163 N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 9