KK74AC192

TECHNICAL DATA KK74AC192 Presettable BCD/Decade UP/DOWN Counter High-Speed Silicon-Gate CMOS The KK74AC192 is identical in pinout to the LS/ALS192, HC/HCT192. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TCD) and Terminal Count Up (TCU) Outputs are provided to enable cascading of both up and down counting functions. The TCD output produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TCU and TCD outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA, 0.1 µA @ 25°C • High Noise Immunity Characteristic of CMOS Devices • Outputs Source/Sink 24 mA ORDERING INFORMATION KK74AC192N Plastic KK74AC192D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND 1 KK74AC192 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74AC192 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 5.5 5.5 8.0 Guaranteed Limits 2 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 -40°C to 8 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 -75 80 µA mA mA µA V Unit V VIL VOUT=0.1 V or VCC-0.1 V V VOH IOUT ≤ -50 µA V VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum Low-Level Output Voltage IOUT ≤ 50 µA * * VIN=VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC FUNCTION TABLE MR PL Inputs CPU X X Mode CPD X X H H Reset(Asyn.) Preset(Asyn.) No Count Count Up Count Down No Count The KK74AC192 can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4: 14, 15, 2 if counting Up, and follow the sequence 15, 14, 13, 12, 11, 10, 9 if counting Down. Logic equations For Terminal Count: TCU = Q0 • Q3 • CPU TCD = Q0 • Q1 • Q2 • Q3 • CPD H X L L L H L H L H L H X = don’t care H H 3 KK74AC192 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL CIN Parameter Maximum Clock Frequency (Figure 1) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, MR to Qn (Figure 5) Propagation Delay, MR to TCU (Figure 6) Propagation Delay, MR to TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Maximum Input Capacitance V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 4.5 Min 88 120 20 13 19 11.5 15 10 15 9.5 15 10 15 9.5 15 10 20 12.5 20 12.5 18 12 19 11.5 20 13 15 8.5 20 13 20 12.5 4.5 Guaranteed Limits 2 5 °C Max -40°C to 85°C Min 40 55 22 14.5 21 13.0 17.0 11.5 17.0 11 17.0 11.5 17.0 11 17 11.5 22 14 22 14 20 13.5 21 13.0 22 14.5 17 10 22 14.5 22 14 Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF Unit Typical @25°C,VCC=5.0 V CPD * Power Dissipation Capacitance 45 pF Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V 4 KK74AC192 TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns) VCC* Symbol tsu th tw tw tw trec trec * Guaranteed Limits 2 5 °C 9 6 -1.0 -1.0 17 12 11 8 14 10 9 12 17 12 -40°C to 8 5 °C 10 7 0 0 21 13 12 9 16 12 10 13 21 14 Unit ns ns ns ns ns ns ns Parameter Minimum Setup Time, Pn to PL (Figure 7) Minimum Hold Time, PL to Pn (Figure 7) Minimum Pulse Width, PL (Figure 4) Minimum Pulse Width, CPU or CPD (Figure 1) Minimum Pulse Width, MR (Figure 5) Minimum Recovery Time, PL to CPU or CPD (Figure 5) Minimum Recovery Time, MR to CPU or CPD (Figure 5) V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms 5 KK74AC192 Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms TIMING DIAGRAM 6 KK74AC192 EXPANDED LOGIC DIAGRAM 7 KK74AC192 N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 8