KK74AC273

TECHNICAL DATA KK74AC273 Octal D Flip-Flop with Common Clock and Reset The KK74AC273 is identical in pinout to the LS/ALS273, HC/HCT273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA; 0.1 µA @ 25°C • High Noise Immunity Characteristic of CMOS Devices • Outputs Source/Sink 24 mA ORDERING INFORMATION KK74AC273N Plastic KK74AC273DW SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Reset L H H H H X = don’t care L Clock X D X H L X X Output Q L H L no change no change 1 KK74AC273 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74AC273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 5.5 5.5 8.0 Guaranteed Limits 2 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 -40°C to 8 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 -75 80 µA mA mA µA V Unit V VIL VOUT=0.1 V or VCC-0.1 V V VOH IOUT ≤ -50 µA V VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT ≤ 50 µA * * VIN=VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC 3 KK74AC273 AC ELECTRICAL CHARACTERISTICS (CL=50pF, Input tr=tf=3.0 ns) VCC* Symbol Parameter V Guaranteed Limits 2 5 °C Min fmax tPLH tPLH tPHL CIN Maximum Clock Frequency (Figure 1) Propagation Delay, Clock to Q (Figure 1) Propagation Delay, Clock to Q (Figure 1) Propagation Delay, Reset to Q (Figure 2) Maximum Input Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 90 140 4.0 3.0 4.0 3.0 4.0 3.0 4.5 12.5 9.0 13.0 10.0 13.0 10.0 Max -40°C to 8 5 °C Min 75 125 3.0 2.5 3.5 2.5 3.5 2.5 4.5 14.0 10.0 14.5 11.0 14.0 10.5 Max MHz ns ns ns pF Unit Typical @25°C,VCC=5.0 V CPD * Power Dissipation Capacitance 50 pF Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns) VCC* Symbol tsu th tw tw trec * Guaranteed Limits 2 5 °C 5.5 4.0 0 1.0 5.5 4.0 5.5 4.0 3.5 2.0 -40°C to 8 5 °C 6.0 4.5 0 1.0 6.0 4.5 6.0 4.5 4.5 3.0 Unit ns ns ns ns ns Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Data to Clock (Figure 3) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Minimum Recovery Time, Reset to Clock (Figure 2) V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V 4 KK74AC273 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM 5 KK74AC273 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6