KK74AC323

TECHNICAL DATA 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS The KK74AC323 is identical in pinout to the LS/ALS323, HC/HCT323. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The KK74AC323 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA; 0.1 µA @ 25°C • High Noise Immunity Characteristic of CMOS Devices • Outputs Source/Sink 24 mA KK74AC323 ORDERING INFORMATION KK74AC323N Plastic KK74AC323DW SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND 1 KK74AC323 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74AC323 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 Guaranteed Limits 2 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 ±0.6 -40°C to 8 5 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 ±6.0 µA µA V Unit V VIL VOUT=0.1 V or VCC-0.1 V V VOH IOUT ≤ -50 µA V VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT ≤ 50 µA * * VIN= VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA VIN=VCC or GND IIN IOZ Maximum Input Leakage Current Maximum ThreeState Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN (OE)= VIH or VIL VIN =VCC or GND VOUT =VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND IOLD IOHD ICC 5.5 5.5 5.5 8.0 75 -75 80 mA mA µA * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC 3 KK74AC323 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol Parameter V Guaranteed Limits 2 5 °C Min fmax tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ CIN Maximum Clock Frequency (Figure 1) Propagation Delay, Clock to QA’ or QH’ (Figure 1) Propagation Delay, Clock to QA’ or QH’ (Figure 1) Propagation Delay, Clock to QA thru QH (Figure 1) Propagation Delay, Clock to QA thru QH (Figure 1) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Maximum Input Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 90 130 8.5 5.5 8.5 5.5 9.0 6.0 10.0 6.5 7.0 4.5 7.0 5.0 6.5 3.5 5.5 3.5 4.5 20.5 14.0 21.5 14.5 20.5 14.5 23.0 16.0 18.0 12.5 18.0 12.5 18.5 14.0 17.0 12.5 Max -40°C to 8 5 °C Min 80 105 7.0 4.5 7.0 5.0 7.5 5.0 8.5 6.0 6.0 4.0 6.0 4.0 5.5 3.0 4.5 2.0 4.5 22.0 15.0 23.0 16.0 22.5 16.0 24.5 17.5 19.5 13.5 20.5 14.0 19.5 15.0 19.0 13.5 Max MHz ns ns ns ns ns ns ns ns pF Unit Typical @25°C,VCC=5.0 V CPD * Power Dissipation Capacitance 170 pF Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V 4 KK74AC323 TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol tsu tsu tsu tsu th th th th tw tw * Guaranteed Limits 2 5 °C 8.0 5.0 5.5 3.5 6.5 4.0 6.5 4.0 0.5 1.0 0 1.0 0 1.0 0 1.0 4.5 3.5 4.5 3.5 -40°C to 8 5 °C 8.5 5.5 6.0 4.0 7.0 4.5 7.0 4.5 0.5 1.0 0 1.0 0.5 1.0 0 1.0 5.0 3.5 5.0 3.5 Unit ns ns ns ns ns ns ns ns ns ns Parameter Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Minimum Setup Time, Data Inputs PA thru PH to Clock (Figure 4) Minimum Setup Time, Data Inputs SA, SH to Clock (Figure 4) Minimum Setup Time, Reset to Clock (Figure 2) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Hold Time, Clock to Data Inputs PA thru PH (Figure 4) Minimum Hold Time, Clock to Data Inputs SA, SH (Figure 4) Minimum Hold Time, Clock to Reset (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Voltage Range 3.3 V is 3.3 V ±0.3 V Voltage Range 5.0 V is 5.0 V ±0.5 V 5 KK74AC323 FUNCTION TABLE Inputs Mode Reset Mode Select S2 Reset L L L Shift Right H H H Shift Left H H H Parallel Load Hold H H H H X L H L L L H H H H L L L S1 L X H H H H L L L H L L L Output Enables OE1 L L X H X L H X L X H X L OE2 L L X X H L X H L X X H L X X X X Clock Serial Inputs DA D H X X X D D D X X X X X X X X X X X X X D D D X X X X L L L L L L L L L L L L L L L L L L L D D D QB QB QB PA PA PA PA L L L QG QG QG D D D PH PH PH PH Response PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’ QA QB QC QD QE QF QG QH QA through QH=Z Shift Right: QA through QH=Z; F A; F A FB; etc DA Shift Right: QA through QH=Z; FA; FA FB; etc DA Shift Right: DA FA =QA; FB =QB; etc FA Shift Left: QA through QH=Z; FH; FH FG; etc DH Shift Left: QA through QH=Z; F H; F H FG; etc DH Shift Left: DH FH =QH; FG =QG; etc FH Parallel Load:PN FN Hold: QA through QH=Z; FN=FN Hold: QA through QH=Z; FN=FN Hold: QN =QH Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. 6 KK74AC323 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform 7 KK74AC323 EXPANDED LOGIC DIAGRAM 8 KK74AC323 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 9