TECHNICAL DATA
KK74HC21A
Dual 4-Input AND Gate
The KK74HC21A is high-speed Si-gate CMOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION KK74HC21AN Plastic KK74HC21AD SOIC TA = -55° to 125° C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
A1
B1 Y1
A1 B1
C1 D1
1 2 3 4 5 6 7
14 13 12 11 10 9 8
V CC
D2 C2
C1
B2 A2 Y2
A2 B2 Y2 C2 D2
Y1 GND
FUNCTION TABLE
Inputs
A
L
X
X
X
H
X = don’t care
Output
С
X
X
L
X
H
B
X
L
X
X
H
D
X
X
X
L
H
Y
L
L
L
L
H
PIN 14 =VCC PIN 7 = GND
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KK74HC21A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
2
KK74HC21A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions VCC V Guaranteed Limit 2 5 °C to -55°C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.92 2.92 4.42 5.92 2.48 3.98 5.48 0.09 0.09 0.09 0.09 0.26 0.26 0.26 -0.1 0.1 4.0 ≤85 °C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 2.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.1 0.33 0.33 0.33 -1.0 1.0 40 ≤125 °C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 2.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.1 0.4 0.4 0.4 -1.0 1.0 160 µA µA µA V V Unit
VIH
Minimum High-Level Input Voltage
2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 VIN=VIH or VIL ⎢IOUT⎢ = -50 µA 2.0 3.0 4.5 6.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 6.0
VIL
Maximum Low -Level Input Voltage
V
VOH
Minimum High-Level Output Voltage
V
VIN=VIH or VIL ⎢IOUT⎢ = -2.4 mА VIN=VIH or VIL ⎢IOUT⎢ = -4 mА VIN=VIH or VIL ⎢IOUT⎢ = -5.2 mА VOL Maximum Low-Level Output Voltage VIN= VIH or VIL ⎢IOUT⎢ = 50 µA
VIN=VIH or VIL ⎢IOUT⎢ = 2.4 mА VIN=VIH or VIL ⎢IOUT⎢ = 4 mА VIN=VIH or VIL ⎢IOUT⎢ = 5.2 mА IIL IIH ICC Maximum Low-Level Input Leakage Current Maximum High-Level Input Leakage Current Maximum Quiescent Supply Current VIN= 0 V VIN= VCC VIN=VCC or 0 V
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KK74HC21A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC Symbol Parameter V Guaranteed Limit 2 5 °C to -55°C 110 22 19 75 15 13 10 ≤85°C ≤125°C Unit
tPHL, tPLH
Maximum Propagation Delay (Figure 1)
2.0 4.5 6.0 2.0 4.5 6.0 5.0
140 28 24 95 19 16 10
165 33 28 110 22 19 10
ns
tTHL, tTLH
Maximum Output Transition Time (Figure 1) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate)
ns
CIN
pF
TA=25°C,VCC=5.0 V 50 pF
CPD
Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
tLH
0.9 0.9 V2
tHL V1
Input
0.1
V2
0.1
GND
VCC
tPLH
0.9
tPHL
0.9
V2
Output
V2
0.1
0.1
0V
tTLH
V1 = 0.5 VCC
tTHL
Figure 1. Switching Waveforms
VCC
VI PULSE GENERATOR RT D EVI CE UNDER TEST
VO
Termination resistance RT – should be equal to ZOUT of pulse generators
CL 50 pF
Figure 2. Test Circuit
4
KK74HC21A
N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA)
A 14 8 B 1 7
Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78
F
L
D F
C -T- SEATING N G D 0.25 (0.010) M T K
PLAN E
G H
H J
M
J K L M N
NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e.
D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm
8
A 14
Symbol A
MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25
MAX 8.75 4 1.75 0.51 1.27
H
B
P
B C
1
G
7 C R x 45
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLAN E
H
J F M
J K M P R
8° 0.25 0.25 6.2 0.5
NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e.
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