KK74HC573A

TECHNICAL DATA KK74HC573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS N SUFFIX PLASTIC DIP The KK74HC573A is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when LE is high. When LE goes low, data meeting the setup and hold time becomes latched. • • • • Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices 20 1 20 1 DW SUFFIX S O IC ORDERING INFORMATION KK74HC573AN KK74HC573ADW Plastic DIP SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 19 18 17 16 15 14 13 12 OE D0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE D0 D1 D2 DATA INP UT S D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NON INVE RT ING OUT P UT S D1 D2 D3 D4 D5 D6 D7 GND LE 11 OE 1 FUNCTION TABLE Inputs OE LE H H L X Output D H L X X Q H L no change Z PIN 20=VCC PIN 10 = GND L L L H H= high level L = low level X = don’t care Z = high impedance 1 KK74HC573A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1.5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC573A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VC C Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 ≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 ≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 µA µA V Unit V Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT ≥ VCC-0.1 V ⎢IOUT⎢≤ 20 µA VOUT⎢ ≤ 0.1 V ⎢IOUT⎢ ≤ 20 µA VIN=VIH ⎢IOUT⎢ ≤ 20 µA VIN=VIH ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤ 7.8 mA V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL ⎢IOUT⎢ ≤ 20 µA VIN= VIL ⎢IOUT⎢ ≤ 6.0 mA ⎢IOUT⎢ ≤7.8 mA IIN IOZ Maximum Input Leakage Current Maximum Three State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN =VIH VOUT= VCC or GND VIN=VCC or GND IOUT=0µA ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 µA 3 KK74HC573A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay, LE to Q (Figures 2 and 5) Maximum Propagation Delay, OE to Q (Figures 3 and 6) Maximum Propagation Delay, OE to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Enabled Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 150 30 26 160 32 27 150 30 26 150 30 26 60 12 10 10 15 ≤85°C 190 38 33 200 40 34 190 38 33 190 38 33 75 15 13 10 15 ≤125°C 225 45 38 240 48 41 225 45 38 225 45 38 90 18 15 10 15 Unit ns tPLH, tPHL ns tPLZ, tPHZ ns tPZH, tPZL ns tTLH, tTHL ns CIN COUT pF pF Typical @25°C,VCC=5.0 V 23 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol tSU Parameter Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time, Latch Enable to Input D (Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25 °C to -55°C 50 10 9 5 5 5 75 15 13 1000 500 400 Guaranteed Limit ≤85°C 65 13 11 5 5 5 95 19 16 1000 500 400 ≤125°C 75 15 13 5 5 5 110 22 19 1000 500 400 Unit ns th ns tw ns tr, tf ns 4 KK74HC573A VCC 0В tw t PLH Q t TH L 50% tr D tPLH Q t TLH 50% 10% 90% 90% 50% 10% tf LE VCC 0В t PHL 50% t PHL Figure 1. Switching Waveforms OE t PZL Q t PZH Q 50% 50% 50% Figure 2. Switching Waveforms VCC 0В HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE D 50% t PLZ 10% t PHZ 90% VCC 0В t su th 50% LE VCC 0В Figure 3. Switching Waveforms * Includes all probe and jig capacitance TEST POINT DEVICE UNDER TEST Figure 4. Switching Waveforms * Includes all probe and jig capacitance TEST POINT 1k CL * OUTPUT * CL DEVICE UNDER TEST OUTPUT Co nnect to V CC when testing tPLZ and tPZL Co nnect to GND when testing tPHZ and tPZH Figure 5. Test Circuit Figure 6. Test Circuit EXPANDED LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 KK74HC573A N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6