KK74HCT109AN

TECHNICAL DATA KK74HCT109A Dual J-K Flip-Flop with set and Reset High-Performance Silicon-Gate CMOS The KK74HCT109A is identical in pinout to the LS/ALS109. The KK74HCT109A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT109AN Plastic KK74HCT109AD SOIC TA = -55° to 125° C for all packages. PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H PIN 16=VCC PIN 8 = GND Reset H L L H H H H Clock X X X J X X X L H L H K X X X L L H H Output Q H L H * Q L H H* H L Toggle No Change H L H H L X X No Change X = Don’t care * Both outputs will remain high as long as Set and Reset are low., but the output states are unpredictable if Set and Reset go high simultaneously. 1 KK74HCT109A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond witch damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns 2 KK74HCT109A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 2 5 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 Unit VIH Minimum HighLevel Input Voltage Maximum Low -Level Input Voltage Minimum HighLevel Output Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 V VIL V VOH V 4.5 4.5 5.5 3.98 0.1 0.1 3.84 0.1 0.1 3.7 0.1 0.1 V VOL Maximum LowLevel Output Voltage VIN= VIL or VIH ⎢IOUT⎢ ≤ 20 µA VIN= VIL or VIH ⎢IOUT⎢ ≤4.0 mA 4.5 5.5 0.26 ±0.1 0.33 ±1.0 0.4 ±1.0 µA IIN Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND ICC VIN=VCC or GND IOUT=0µA 5.5 4.0 40 80 µA ∆ICC VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA 5.5 ≥-55°C 2.9 25°C to 125°C 2.4 µA This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 3 KK74HCT109A AC ELECTRICAL CHARACTERISTICS (VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 2 5 °C to -55°C 30 35 46 15 10 ≤85 °C 24 44 58 19 10 ≤125 °C 20 53 69 22 10 Unit fmax tPLH, tPHL tPHL tTLH, tTHL CIN Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay , Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Flip-Flop) MHz ns ns ns pF Typical @25°C,VCC=5.0 V 60 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC+∆ICCVCC TIMING REQUIREMENTS (VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol tSU th trec Parameter Minimum Setup Time, J or K to Clock (Figure 3) Minimum Hold Time, Clock to J or K (Figure 3) Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Set or Reset (Figure 2) Minimum Pulse Width,Clock (Figure 1) Maximum Input Rise and Fall Times (Figure 1) 25 °C to -55°C 20 5 5 ≤85°C 25 5 5 ≤125°C 30 5 5 Unit ns ns ns tw tw tr, tf 16 16 500 20 20 500 24 24 500 ns ns ns 4 KK74HCT109A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM 5 KK74HCT109A N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6