KK74HCT138A

TECHNICAL DATA KK74HCT138A 1-of-8 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The KK74HCT138A is identical in pinout to the LS/ALS138. The KK74HCT138A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The KK74HCT138A decodes a three-bit Address to one-of-eight active-lot outputs. This device features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT138AN Plastic KK74HCT138AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs CS1 CS2 CS3 XXH XHX LXX H H H H H H H H L L L L L L L L L L L L L L L L A2 A1 A0 XXX XXX XXX L L L L H H H H L L H H L L H H L H L H L H L H Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H HHHHH H H H HHHHH H H H HHHHH L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L PIN 16 =VCC PIN 8 = GND H = high level (steady state) L = low level (steady state) X = don’t care 1 KK74HCT138A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 2) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT138A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 2 5 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 4.0 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 40 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 ±1.0 160 µA µA V Unit VIH VIL VOH Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum LowLevel Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0µA VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA ∆ICC ≥-55°C 25°C to 125°C 2.4 mA 5.5 2.9 3 KK74HCT138A AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 2 5 °C to -55°C 30 27 30 15 10 ≤85°C ≤125°C Unit tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL CIN Maximum Propagation Delay, Input A to Output Y (Figures 1 and 4) Maximum Propagation Delay , CS1 to Output Y (Figures 2 and 4) Maximum Output Transition Time , CS2 or CS3 to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 2 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output) 38 34 38 19 10 45 41 45 22 10 ns ns ns ns pF Typical @25°C,VCC=5.0 V 51 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Figure 2. Switching Waveforms 4 KK74HCT138A Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM 5 KK74HCT138A N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6