KK74HCT164AN

TECHNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS KK74HCT164A The KK74HCT164A may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The KK74HCT164A is identical in pin out to the LS/ALS164. • • • • TTL/NMOS-Compatible Input Levels. Outputs Directly Interface to CMOS, NMOS and TTL. Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT164AN Plastic KK74HCT164AD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND Reset L H H H FUNCTION TABLE Inputs Clock X Outputs QA QB ... QH L L ... L no change D QAn ... QGn D QAn ... QGn A1 X X H D A2 X X D H D = data input X = don’t care QAn - QGn = data shifted from the previous stage on a rising edge at the clock input. 1 KK74HCT164A MAXIMUM RATINGS* Parameter Value DC Supply Voltage (Referenced to GND) -0.5 to +7.0 DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 DC Input Current, per Pin ±20 DC Output Current, per Pin ±25 DC Supply Current, VCC and GND Pins ±50 Power Dissipation in Still Air, Plastic DIP+ 750 SOIC Package+ 500 Tstg Storage Temperature -65 to +150 TL Lead Temperature, 1 mm from Case for 10 260 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from -55° to 125°C SOIC Package: : - 7 mW/°C from -55° to 125°C Symbol VCC VIN VOUT IIN IOUT ICC PD Unit V V V mA mA mA mW °C °C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA t r, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT164A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VC C Guaranteed Limit 25 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 Unit Symbol Parameter Test Conditions V VIH VIL VOH VOL IIN ICC ∆ICC Minimum High- VOUT=0.1 V or VCC-0.1 V Level Input ⎢IOUT⎢≤ 20 µA Voltage Maximum Low - VOUT= VCC-0.1 V Level Input ⎢IOUT⎢ ≤ 20 µA Voltage Minimum High- VIN=VIH or VIL Level Output ⎢IOUT⎢ ≤ 20 µA Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA Maximum Low- VIN=VIH Level Output ⎢IOUT⎢ ≤ 20 µA Voltage VIN=VIH ⎢IOUT⎢ ≤ 4.0 mA Maximum Input VIN=VCC or GND Leakage Current Maximum or GND VIN=VCC Quiescent Supply IOUT=0µA Current (per Package) Additional VIN = 2.4 V, Any One Quiescent Supply Input Current VIN=VCC or GND, Other Inputs IOUT=0µA 4.5 5.5 4.5 5.5 4.5 5.5 V V V 4.5 4.5 5.5 3.98 0.1 0.1 3.84 0.1 0.1 3.7 0.1 0.1 V 4.5 5.5 5.5 0.26 ±0.1 1.0 0.33 ±1.0 10 0.4 ±1.0 40 µA µA ≥-55°C 25°C to 125°C 2.4 mA 5.5 2.9 3 KK74HCT164A AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=6.0 ns) Symbol Parameter Guaranteed Limit 25 °C ≤85°C ≤125 to °C -55°C 30 24 20 38 41 15 48 52 19 10 Typical @25°C,VCC=5.0 V Unit fmax tPLH, tPHL tPHL tTLH, tTHL CIN Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay,Clock to Q (Figures 1 and 4) Maximum Propagation Delay,Reset to Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC MHz ns ns ns pF 58 63 22 CPD 360 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) Symbol tSU th Parameter Minimum Setup Time,A1 or A2 to Clock (Figure 3) Minimum Hold Time, Clock to A1 or A2 (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Clock (Figure 1) Guaranteed Limit 25 °C to ≤85°C ≤125°C -55°C 7 8 9 5 5 5 Unit ns ns trec 5 5 5 ns tw tw 12 12 15 15 20 20 ns ns 4 KK74HCT164A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms TIMING DIAGRAM Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM 5 KK74HCT164A N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6