KK74HCT21A

TECHNICAL DATA KK74HCT21A Dual 4-Input AND Gate The KK74HCT21A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL) . The device provide the Dual 4-input AND function. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HCT21AN Plastic KK74HCT21AD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT A1 B1 Y1 A1 B1 C1 D1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V CC D2 C2 C1 B2 A2 Y2 A2 B2 Y2 C2 D2 Y1 GND FUNCTION TABLE Inputs A B X L X X H Output С X X L X H D X X X L H Y L L L L H PIN 14 =VCC PIN 7 = GND L X X X H X = don’t care 1 KK74HCT21A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 4.5 0 -55 0 0 0 Max 5.5 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT21A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V Guaranteed Limit 2 5 °C to -55°C 2.0 2.0 0.8 0.8 4.42 5.42 3.98 0.09 0.09 0.26 -0.1 0.1 4.0 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 -1.0 1.0 40 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.70 0.1 0.1 0.4 -1.0 1.0 160 µA µA µA V V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VIN=VIH or VIL ⎢IOUT⎢ = - 50 µA VIN= VIH or VIL ⎢IOUT⎢ = - 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 5.5 VIL V VOH V VOL Maximum Low-Level Output Voltage IIL IIH ICC Maximum Low-Level Input Leakage Current Maximum High-Level Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Additional Quiescent Supply Current on input pin VIN= VIH or VIL ⎢IOUT⎢ = 50 µA VIN= VIH or VIL ⎢IOUT⎢ = 4.0 mA VIN= 0 V VIN= VCC VIN=VCC or 0 V IOUT=0 µA VIN=3.4 V any one input, VIN= 0 V or VCC others inputs ICCT 5.5 ≤-55°C 2.9 2 5 °C ÷ -125°C 2.4 mА 3 KK74HCT21A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter V Guaranteed Limit 2 5 °C to -55°C 27 15 10 ≤85°C ≤125°C Unit tPHL, tPLH tTHL, tTLH CIN Maximum Propagation Delay (Figure 1) Maximum Output Transition Time (Figure 1) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) 4.5 4.5 5.0 34 19 10 41 22 10 ns ns pF TA=25°C,VCC=5.0 V 50 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC tLH 0.9 0.9 V1 tHL VIH Input 0.1 V1 0.1 GND tPLH 0.9 tPHL VOH 0.9 V1 Output V1 0.1 0.1 0V tTLH V1 = 1.3 V VI = 3.0 V tTHL Figure 1. Switching Waveforms VCC VI PULSE GENERATOR RT D EVI CE UNDER TEST VO Termination resistance RT – should be equal to ZOUT of pulse generators CL 50 pF Figure 2. Test Circuit 4 KK74HCT21A N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 5