KK74HCT241ADW

TECHNICAL DATA KK74HCT241A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS The KK74HCT241A is identical in pinout to the LS/ALS241. The KK74HCT241A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two output enables. Enable A is active-low and Enable B is active-high. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT241AN Plastic KK74HCT241ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Enable A PIN 20=VCC PIN 10 = GND L L H A L H X Output YA L H Z Inputs Enable B H H L B L H X Output YB L H Z X = don’t care Z = high impedance 1 KK74HCT241A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT241A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 2 5 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 Unit VIH Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage VOUT= VCC-0.1 V ⎢IOUT⎢≤ 20 µA VOUT= 0.1 V ⎢IOUT⎢ ≤ 20 µA VIN= VIH ⎢IOUT⎢ ≤ 20 µA VIN= VIH ⎢IOUT⎢ ≤ 6.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 V VIL V VOH V 4.5 4.5 5.5 3.98 0.1 0.1 3.84 0.1 0.1 3.7 0.1 0.1 V VOL Maximum LowLevel Output Voltage VIN = VIL ⎢IOUT⎢ ≤ 20 µA VIN= VIL ⎢IOUT⎢ ≤ 6.0 mA 4.5 5.5 5.5 0.26 ±0.1 ±0.5 0.33 ±1.0 ±5.0 0.4 ±1.0 ±10.0 µA µA IIN IOZ Maximum Input Leakage Current Maximum three State Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND Output in High-Impedance State VIN = VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0µA ICC 5.5 4.0 40 160 µA ∆ICC VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA 5.5 ≥-55°C 2.9 25°C to 125°C 2.4 mA NOTE: Total Supply Current = ICC + ∑∆ICC 3 KK74HCT241A AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 2 5 °C to -55°C 23 30 26 12 10 15 ≤85°C ≤125°C Unit tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tTLH, tTHL CIN COUT Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Enable Output) 29 38 33 15 10 15 35 45 39 18 10 15 ns ns ns ns pF pF Typical @25°C,VCC=5.0 V 55 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Figure 2. Switching Waveforms 4 KK74HCT241A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 of the Device) 5 KK74HCT241A N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6