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KK74LS07N

KK74LS07N

  • 厂商:

    KODENSHI(可天士)

  • 封装:

  • 描述:

    KK74LS07N - Hex Non-Inverted Buffers with Open- Collector Outputs - KODENSHI KOREA CORP.

  • 数据手册
  • 价格&库存
KK74LS07N 数据手册
TECHNICAL DATA KK74LS07 Hex Non-Inverted Buffers with OpenCollector Outputs This device contains hex non inverted buffers with open-collector. • High Output Voltage 30 V • High Speed tPD = 12 ns • Low Power Dissipation PD = 13 mW per Gate ORDERING INFORMATION KK74LS07N Plastic KK74LS07D SOIC TA = 0° to 70° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT Y=A FUNCTION TABLE Inputs A H L PIN 14 =VCC PIN 7 = GND Output Y H L 1 KK74LS07 MAXIMUM RATINGS* Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 5.5 30 -65 to +150 Unit V V V °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL VOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Current Ambient Temperature Range 0 Parameter Min 4.75 2.0 0.8 30 40 +70 Max 5.25 Unit V V V V mA °C DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK IOH VOL IIH IIL ICC Parameter Input Clamp Voltage High Level Output Current Low Level Output Voltage High Level Input Current Low Level Input Current Supply Current Test Conditions VCC = 4.75, IIN = -18 mA VCC = 4.75, VOH= 5.25 VCC = 4.75, IOL = 16 mA VCC = 4.75, IOL = 40 mA VCC = 5.25, VIN = 2.7 V VCC = 5.25, VIN = 5.5 V VCC = 5.25, VIN = 0.4 V VCC = 5.25 Total with outputs high Total with outputs low Min Max -1.5 250 0.4 0.7 20 1 -0.2 14 45 µA mA mA mA Unit V µA V 2 KK74LS07 RL = 100 Ω,tr = 15 ns, tf = 6.0 ns) Symbol tPLH tPHL AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF, Parameter Propagation Delay, Input A to Output Y Propagation Delay, Input A to Output Y Min Max 10 30 Unit ns ns Figure 1. Switching Waveforms NOTE A. CL includes probe and jig capacitance. Figure 2. Test Circuit 3 KK74LS07 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 4
KK74LS07N 价格&库存

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