KK74LS164D

TECHNICAL DATA KK74LS164 8-Bit Serial-Input/Parallel-Output Shift Register This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered clocking occurs or the low-to-high level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. • Gated (Enable/Disable) Serial Inputs • Fully Buffered Clock and Serial Inputs • Asynchronous Clear ORDERING INFORMATION KK74LS164N Plastic KK74LS164D SOIC TA =0° to 70°C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Reset L H H H PIN 14 =VCC PIN 7 = GND Clock X A1 A2 XX XX HD DH L Outputs QA QB ... QH L ... L no change D QAn ... QGn D QAn ... QGn H LL L QAn ... QGn D = data input X = don’t care QAn - QGn = data shifted from the previous stage on a rising edge at the clock input. 1 KK74LS164 MAXIMUM RATINGS* Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 7.0 5.5 -65 to +150 Unit V V V °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL TA fclock tsu th tw tw trec Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Ambient Temperature Range Clock Frequency Setup Time, A1 or A2 to Clock Hold Time, Clock to A1 or A2 Pulse Width, Clock Pulse Width, Reset Recovery Time 0 0 15 5 20 20 5 Parameter Min 4.75 2.0 0.8 -0.4 8.0 +70 25 Max 5.25 Unit V V V mA mA °C MHz ns ns ns ns ns DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK VOH VOL IIH IIL IO ICC Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Output Short Circuit Current Supply Current Test Conditions VCC = min, IIN = -18 mA VCC = min, IOH = -0.4 mA VCC = min, IOL = 4 mA VCC = min, IOL = 8 mA VCC = max, VIN = 2.7 V VCC = max, VIN = 7.0 V VCC = max, VIN = 0.4 V VCC = max, VO = 0 V (Noote 1) VCC = max (Note 2) -20 2.7 0.4 0.5 20 0.1 -0.4 -100 27 mA mA mA mA mA Min Max -1.5 Unit V V V Note 1: Not more than one output should be shorted at a time, and duration should not exceed one second. Note 2: ICC is measured with outputs open, serial inputs grouned, the clock input at 2.4 V, and a momentary ground, then 4.5 V applied. 2 KK74LS164 AC ELECTRICAL CHARACTERISTICS (TA=25°C, VCC = 5.0 V, CL = 15 pF, RL = 2 kΩ, tr =15 ns, tf = 6.0 ns) Symbol tPLH tPHL tPHL tsu th tw tw Parameter Propagation Delay Time, Clock to Q Propagation Delay Time, Clock to Q Propagation Delay Time, Reset to Q Setup Time, A1 or A2 to Clock Hold Time, Clock to A1 or A2 Pulse Width, Clock Pulse Width, Reset 15 5 20 20 Min Max 27 32 36 Unit ns ns ns ns ns ns ns Figure 1. Switching Waveforms Figure 2. Switching Waveforms NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 3. Switching Waveform Figure 4. Test Circuit 3 KK74LS164 TIMING DIAGRAM 4 KK74LS164 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 5