KK74LV164N

TECHNICAL DATA 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER The KK74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the KK74HC/HCT164. The KK74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (DSA, DSB ) that existed one set-up time prior to the rising clock edge. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 1.2 to 5.5 V • Low Input Current: 1.0 µA, 0.1 µА at Т = 25 °С • Output Current: 6 mA at VCC = 3.0 V; 12 mA at VCC = 4.5 V • High Noise Immunity Characteristic of CMOS Devices KK74LV164 N S UFF IX PL ASTI C DIP 14 1 14 D S UFF IX SO 1 ORDERING INFORMATION KK74LV164N KK74LV164D Plastic SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT DSA DSB 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC Q7 Q6 Q5 Q4 MR CP LOGIC DIAGRAM Q0 Q1 1 SER IAL D SA DATA 2 IN P UT S DS B Q2 DATA 2 Q0 4 Q1 5 Q2 6 Q3 10 Q4 11 Q5 12 Q6 CP 8 13 Q7 PAR ALLE L DATA OUT P UT S Q3 GND FUNCTION TABLE Inputs Outputs DSB X L H L H Q0 L L L L H Q1 ... Q7 L…L Q0 ... Q6 Q0 ... Q6 Q0 ... Q6 Q0 ... Q6 X L L H H MR L H H H H CP X DSA MR 9 PIN 14=VCC PIN 7 = GND H = high voltage level L = low voltage level X = don’t care 1 KK74LV164 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD 1 2 Parameter DC supply voltage DC Input diode current DC Output diode current DC Output source or sink current VCC current GND current Power dissipation per package: * Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds 4 Value -0.5 to + 7.0 ±20 ±50 ±25 ±50 ±50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * 3 Tstg TL * °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, tf DC Supply Voltage Input Voltage Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 1.0 V ≤ VCC < 2.0 V 2.0 V ≤ VCC < 2.7 V 2.7 V ≤ VCC < 3.6 V 3.6 V ≤ VCC ≤ 5.5 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV164 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol VIH Parameter HIGH level input voltage conditions VCC V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL IO = -100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 Guaranteed Limit 25°C to -40°C max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 ±0.1 8.0 0.2 85°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.4 0.55 ±1.0 80 0.5 125°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.5 0.65 ±1.0 160 0.85 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -6.0 mА VI = VIH or VIL IO = -12.0 mА VOL LOW level output voltage VI = VIH or VIL IO = 100 µА V V V VI = VIH or VIL IO = 6.0 mА VI = VIH or VIL IO = 12.0 mА II ICC ICC1 Input current Supply current Supply current VI = VCC or 0 V VI =VCC or 0 V IO = 0 µА VI =VCC – 0.6 V V V µА µА mА 3 KK74LV164 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf= 2.5 ns, RL = 1 kΩ) Test Symbol Parameter conditions V I = 0 V or V 1 Figure 1 and 4 VCC V 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 VI = 0 V or VCC 5.5 min tPHL, tPLH Propagation delay , CP to Qn 100 28 21 17 14 60 19 13 11 9 50 5 5 5 5 70 15 11 9 8 Guaranteed Limit 25°C to -40°C max 150 30 23 18 15 150 30 23 18 15 2 16 22 27 32 7.0 80 130 34 25 20 17 80 22 16 13 11 50 5 5 5 5 100 19 14 11 10 85°C min max 180 39 29 23 19 180 39 29 23 19 1 14 19 24 27 160 41 30 24 20 100 26 19 15 13 50 5 5 5 5 130 24 18 14 12 125°C min max 210 49 36 29 24 210 49 36 29 24 1 12 16 20 24 ns Unit tPHL Propagation delay , MR to VI = 0 V or V1 Qn Figure 1 and 4 ns tw Pulse Width, CP or MR V I = 0 V or V 1 Figure 1 ns tsu Setup Time, DSA or DSB VI = 0 V or V1 to CP Figure 3 ns th Hold Time, DSA or DSB to CP V I = 0 V or V 1 Figure 3 ns trec Recovery Time, MR to CP VI = 0 V or V1 Figure 2 ns fmax Clock Frequency VI = 0 V o r V 1 Figure 1 and 4 MHz CI CPD Input capacitance Power dissipation capacitance pF pF 4 KK74LV164 tw tr CP 10% VM (1 ) tf 90% V1 (2) MR t PHL Q VM (1) V1 (2) GND tw tPLH 1/fmax GND VOH VOL VM (1) t PHL VOH VOL Q VM (1 ) t rec CP VM (1 ) V1 (2) GND Figure 1. Switching Waveforms Figure 2. Switching Waveforms TEST POINT VALID DSA or DSB VM (1 ) V1 (2) GND t su th VM (1 ) DEVICE UNDER TEST OUTPUT RL CL * CP V1 (2) GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Note: (1) (2) Figure 4. Test Circuit VM = 1.5 V at VCC = 2.7 V VM = 0.5 ⋅VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V TIMING DIAGRAM CP DSA DSB MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 5 KK74LV164 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AA) A 14 8 B 1 7 Dimens ion, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AB) Dimens ion, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0° 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLAN E H J F M J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 6