KK74LV273N

TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset The KK74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The KK74LV273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • High Noise Immunity Characteristic of CMOS Devices KK74LV273 N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION KK74LV273N Plastic DIP KK74LV273DW SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM RESET Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK FUNCTION TABLE Inputs Reset L H H PIN 20=VCC PIN 10 = GND Output D X H L Clock X Q L H L no change no change H H L X X H= high level L = low level X = don’t care Z = high impedance 1 KK74LV273 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP *4 SO * 4 Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +7.0 ±20 ±50 ±25 ±50 ±50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * 3 Tstg TL * °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 0 V ≤ VCC ≤ 2.0 V 2.0 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V 3.6 V ≤ VCC ≤ 5.5 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol VIH Parameter HIGH level input voltage conditions VCC V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 25°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 ±0.1 8.0 0.2 min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 Guaranteed Limit -40°C max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 ±0.1 8.0 0.2 min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 85°C max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 ±1.0 80 0.5 125°C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 ±1.0 160 0.85 V Unit VIL LOW level output voltage V VOH HIGH level VI = VIH or VIL output IO = -100 µА voltage V VI = VIH or VIL IO = -6 mА VI = VIH or VIL IO = -12 mА VOL LOW level output voltage VI = VIH or VIL IO = 100 µА V V V VI = VIH or VIL IO = 6 mА VI = VIH or VIL IO = 12 mА II ICC ICC1 Input current Supply current Additional supply current per input VI = VCC or 0 V VI =VCC or 0 V IO = 0 µ А VI = VCC – 0.6V V V µА µА mA 3 KK74LV273 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=2.5 ns) Test Symbol Parameter conditions V I = 0 V or V 1 Figures 1,4 VCC V 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 5.5 min tPHL, tPLH Propagation delay , Clock to Q max 150 30 22 17 14 160 40 30 23 19 6.0* 40* Guaranteed Limit -40°C to 25°C 85°C min max 150 32 24 19 16 160 44 33 26 22 125°C min max 150 41 30 24 20 160 56 41 33 28 ns Unit tPHL Propagation delay , Reset to Q V I = 0 V or V 1 Figures 2,4 ns CI CPD * T = 25oC Input capacitance Power dissipation VI = 0 V or VCC capacitance (per flip-flop) pF pF TIMING REQUIREMENTS(CL=50 pF, tr=tf=2.5 ns) Test Symbol tw Parameter Pulse Width, Clock (low or high), Reset (low) conditions V I = 0 V or V 1 Figures 1,2,4 VCC V 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 min 60 28 21 16 12 40 18 13 11 9 5 5 5 5 5 50 5 5 5 5 max 2 17 23 30 32 Guaranteed Limit -40°C to 25°C 70 34 25 20 16 50 22 16 13 11 5 5 5 5 5 50 5 5 5 5 85°C min max 1 14 19 24 27 80 41 30 24 20 60 26 19 15 13 5 5 5 5 5 50 5 5 5 5 125°C min max 1 12 16 20 24 ns Unit tsu Setup Time, Data to Clock VI = 0 V or V1 Figures 3,4 ns trem Removal Time, Reset to Clock V I = 0 V or V 1 Figures 2,4 ns th Hold Time, Clock to Data VI = 0 V or V1 Figures 3,4 ns fc Clock Frequency V I = 0 V or V 1 Figures 1,4 MHz 4 KK74LV273 VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms Figure 2. Switching Waveforms 5 KK74LV273 Figure 3. Switching Waveforms Symbol VCC V1 VM 1,2 1,2 0,6 2,0 2,0 1,0 Level of a signal, V 2,7 2,7 1,5 TEST POINT DEVICE UNDER TEST 3,0 2,7 1,5 4,5 4,5 2,25 OUTPUT CL * * Includes all probe and jig capacitance Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM 6 KK74LV273 N S UFFIX PLAS TIC DIP (MS - 0 0 1 AD) A Dimens ion, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLAN E G H H J M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 3 AC) A 20 11 Dimens ion, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0° 0.1 0.23 10 0.25 8° 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SE AT IN G PL AN E J F M G H J K M P R NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p ro tru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 7