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KKF8594E

KKF8594E

  • 厂商:

    KODENSHI(可天士)

  • 封装:

  • 描述:

    KKF8594E - 512 x 8-bit CMOS EEPROMS with I2C- bus Interface - KODENSHI KOREA CORP.

  • 数据手册
  • 价格&库存
KKF8594E 数据手册
TECHNICAL DATA KKF8594E 512 x 8-bit CMOS EEPROMS with I2Cbus Interface The KKF8594E is а 4-Kbit (512 х 8-bit) floating gate electrically erasable programmable read only memory (ЕЕРPROM). By using an internal redundant storage code it is fault tolerant to single bit errors. This feature dramatically increases reliability compared to conventional ЕЕРRОМ memories. Power consumption is low due to the full СМОS technology used. The programming voltage 1s generated on-chip, using а voltage multiplier. As data bytes are received and transmitted via the serial I2C-bus, а package using eight pins is sufficient. Up to four KKF8594E devices may be connected to the Ic-bus. Chip select is accomplished by two address inputs. Timing of the Erase/Write cycle is done internally, thus no external components are required. Pin 7 must be connected to either VDD or left open-circuit. There is an option of using an external clock or timing the length of an Erase/Write cycle. A write protection input (pin 1) allows disable of write-commands from the master by а hardware signal. When pin 1 is HIGH and one of the upper 256 ЕЕРRОМ cells is addressed, then the data bytes will not be acknowledged by the KKF8594E and the ЕЕРRОМ contents are not changed. KKF8594E Plastic DIP TA = -40° to 85°C PIN ASSIGNMENT • Low Power CMOS maximum active current 2.5 mА • maximum standby current 10 µA • Non-volatile storage of 4-Kbits organized as two pages each 256 х 8-bits • Only one power supply required • On-chip voltage multiplier • Serial input/output bus (I2C) • Write operations byte write mode 8.byte page write mode (minimizes total write time рег byte) • Write-protection input • Read operations sequential read random read • .Extended supply voltage range (2,5 to 6.0 V). • Internal timer for writing (no external components) • .Power-on reset • .High reliability by using а redundant storage code (single bit error correction) • .Endurance 100 k. Tamb = 85 °С • 10 years non-volatile data retention time • Pin and Address compatible to KKF8594E Family and PCx8598X2 Family 1 KKF8594E ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS KKF8594E 8 PIN POSITION DIP MATERIAL plastic CODE SOT97 QUICK REFERENCE DATA SYMBOL VDD IDDR IDDW IDDO PARAMETER Positive supply voltage Supply current READ fSCL= 100 kHz VDD= 3V VDD= 6V fSCL= 100 kHz VDD= 3V VDD= 6V VDD= 3V VDD= 6V CONDITIONS MIN 2.5 MAX 6.0 60 200 0.8 2.5 3.5 10 UNIT V µA µA mA mA µA µA Supply current ERASE/WRITE Supply current STANDBY LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL VDD VI II IO Tstg Tamb PARAMETER positive supply voltage voltage on any input pin current on any input pin output current storage temperature range ambient operating range KKF8594E temperature -40 +40 °C IZII > 500 Ω CONDITIONS MIN -0.3 VSS-0.8 -65 MAX +7.0 VDD+0.8 1 10 +150 UNIT V V mA mA °C 2 KKF8594E CHARACTERISTICS SYMBOL Supply VDD IDDR IDDW IDDO KKF8594E: VDD =4.5 to 5.5 V; VSS = 0 V; Tamb = -40 to +85°C PARAMETER positive supply voltage PCF8594E supply current READ KKF8594E supply current ERASE/WRITE KKF8594E supply current STANDY KKF8594E CONDITIONS MIN MAX UNIT 4.5 fSCL = 100 kHz VDD(max) fSCL = 100 kHz VDD(max) VDD(max) -0.8 0.9VDD VI = VDD or VSS VI = VSS -0.8 0.7VDD 0 -0.8 0.7VDD 10 5.5 200 2.5 10 0.1VDD VDD+0.8 0.3VDD VDD+0.8 ±1 100 7 0.3VDD VDD+0.8 0.4 1 7 - V µA mA µA V V V V µA kHz pF V V V µA pF yrs PTC Input VIL LOW level input voltage VIH HIGH level input voltage SCL Input VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current fSCL clock frequency CI input capacitance SDA Input/Output VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current fSCL clock frequency CI input capacitance Data retention time tS data region time IOH = 3 mA; VDD(min) VOH = VDD VI = VSS Tamb = 55 °C The power-on reset circuit resets the I2C-bus logic with a set-up time ≤ 10 µA. Selection of chip address is achieved by connecting the A1 and A2 inputs to either VSS or VDD. SYMBOL tSW PARAMETER ERASE/WRITE cycle time internal oscillator external clock ERASE/WRITE cycles per byte KKF8594E Endurance Tamb = -40 to +85°C tE/W = 4 to 10 ms Tamb = 22°C; tE/W = 5ms Programming CONDITIONS Supply 4 25 5 5 0 7 10 10 000 100 000 60 300 300 tLOW kHz µs µs ns ns µs ms ms MIN TYP MAX UNIT WRITE CYCLE LIMITS NSW tHIGH tr tf td fP tIL programming frequency LOW time HIGH time rise time fall time delay time 3 KKF8594E LOGIC DIAGRAMM Ucc 1.5-10кОм WP WP Ucc A1 A2 U SS PTC SCL SDA PTC SCL WP Ucc A1 A2 U SS PTC SCL SDA WP A1 A2 U SS WP A1 A2 U SS SDA U SS 4 KKF8594E 5 KKF8594E N S UFFIX PLAS TIC DIP (MS – 0 0 1BA) A 8 5 B 1 4 Dimens ion, mm Symbol A B MIN 8.51 6.1 MAX 10.16 7.11 5.33 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 10° 3.81 8.26 0.36 0.56 1.78 F L C D C -T- SEATING N G D 0.25 (0.010) M T K PL AN E F G M H J H J K L M N NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. 6
KKF8594E 价格&库存

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