ML12009EP

ML12009 ML12011 MECL PLL Components Dual Modulus Prescaler Legacy Device: Motorola MC12009, MC12011 These devices are two–modulus prescalers which will divide by 5 and 6, 8 and 9, respectively. A MECL–to–MTTL translator is provided to interface directly with the Motorola MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. • • • • • • • ML12009 480 MHz (÷5/6), ML12011 550 MHz (÷8/9) MECL to MTTL Translator on Chip MECL and MTTL Enable Inputs 5.0 or –5.2 V Operation* Buffered Clock Input — Series Input RC Typ, 20 Ω and 4.0 pF VBB Reference Voltage 310 mW (Typ) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 (MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using –5.2 V supply, ground Pin 1 (VCCO), Pin 6 (MTTL VCC), and Pin 16 (VCC) and apply –5.2 V to Pin 8 (VEE). If the translator is not required, Pin 6 may be left open to conserve DC power drain. 16 1 SO 16 = -5P PLASTIC PACKAGE CASE 751B 16 1 P DIP 16 = EP PLASTIC PACKAGE CASE 648 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 16 SOIC 16 P DIP 16 SO 16W MC12009P MC12009D MC12011P MC12011D ML12009EP ML12009-5P ML12011EP ML12011-5P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. MAXIMUM RATINGS Characteristic Symbol Rating Unit (Ratings above which device life may be impaired) Power Supply Voltage (VCC = 0) Input Voltage (VCC = 0) Output Source Current Continuous Surge Storage Temperature Range VEE Vin IO 50 100 Tstg –65 to 175 °C –8.0 0 to VEE Vdc Vdc mAdc PIN CONNECTIONS VCCO Q Q (–) (+) MTTL VCC MTTL Output VEE 1 2 3 4 5 6 7 8 (Top View) 16 VCC 15 Clock 14 VBB 13 E1 MECL 12 E2 MECL 11 E3 MECL 10 E4 MECL 9 E5 MECL (Recommended Maximum Ratings above which performance may be degraded) Operating Temperature Range ML12009, ML12011 DC Fan–Out (Note 1) (Gates and Flip–Flops) TA n –30 to 85 70 °C — NOTES: 1. AC fan–out is limited by desired system performance. Page 1 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 1. Logic Diagrams ML12009 MTTL E5 9 MTTL E4 10 MECL E3 11 MECL E2 12 MECL E1 13 D Q1 D Q2 D Q3 MECL to MTTL Translator C Q1 C C Q3 VBB 14 Recommended Circuitry For ac coupled Inputs. 15 1000 pF Clock Input 1.0 k 0.1 µF 3 Q3 2 Q3 54 +– 7 MTTL Out ML12011 MTTL E5 9 MTTL E4 10 MECL E3 11 MECL E2 12 MECL E1 13 15 D Q1 D Q2 D Q3 C C C VBB 14 0.1 µF Q4 Toggle Flip Flop C Q4 MECL to MTTL Translator Recommended Circuitry For ac coupled Inputs. 1000 pF Clock Input 1.0 k 32 Q4 Q4 54 +– 7 MTTL Out Figure 2. Typical Frequency Synthesizer Application fref Phase Detector MC4044/ML4044 Low–Pass Filter Voltage–Controlled Oscillator MC1648/ML1648 fout Modulus Enable Line Counter Control Logic MC12014 Zero Detect Line fout Np Programmable Counter MC4016/ML4016 Counter Reset Line A Programmable Counter MC4016/ML4016 ML12009 ML12011 ML12013 Page 2 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 2b Generic block diagram showing prescaler connection to PLL Device Prescaler Fout Fin PLL ML145146 ML145158 ML145159 ML12009/11 MC in MC VCO Loop Filter Figure 2b shows a generic block diagram of connecting a prescaler to a PLL device that supports dual modulus controls. Applicataion not AN535 describes using a two–modulus prescaler technique. By using prescaler higher frequencies can be achieved than by a single CMOS PLL device. Page 3 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.) Test Limits Pin Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 –65 –1.120 –1.120 –1.655 –1.655 –20 –65 –1.100 –1.100 –2.8 –1.990 –1.990 –1.675 –1.675 –4.26 –1.020 –1.020 –1.630 –1.630 –20 –65 –0.890 –0.890 –10 –10 –10 –10 –1.6 –1.6 1.7 1.7 0.7 –30°C Min –88 5.2 375 375 375 375 6.0 6.0 3.0 100 100 –10 –10 –10 –10 –1.6 –1.6 –1.360 –1.000 –1.000 –2.6 –1.950 –1.950 –1.650 –1.650 –4.40 –0.950 –0.950 –1.595 –1.595 –20 Clock Input VIHmax VILmin –1.160 –0.810 –0.810 –0.930 –0.930 –2.4 –1.925 –1.925 –1.615 –1.615 –4.48 Vdc Vdc mAdc Vdc –0.700 –0.700 2.0 2.0 1.0 Max Min –80 5.2 250 250 250 250 6.0 6.0 3.0 100 100 –10 –10 –10 –10 –1.6 –1.6 2.0 2.0 1.0 25°C Max Min –80 5.2 250 250 250 250 6.4 6.4 3.6 100 100 µAdc µAdc 85°C Max Unit mAdc mAdc µAdc Characteristic Power Supply Drain Current Symbol ICC1 ICC2 IinH1 Input Current IinH2 IinH3 IinH4 Leakage Current IinL1 mAdc IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 3) IOS mAdc Vdc Vdc NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. Page 4 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature –30°C 25°C 85°C Pin Under Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 5 4 4 5 11,12,13 11,12,13 4 11,12,13 11,12,13 5 11,12,13 11,12,13 11,12,13 11,12,13 7 Clock Input VIHmax VILmin 9,10 9,10 9,10 9,10 9 10 4 15 11 12 13 5 5 4 4 4 5 9 10 5 VIHmax –0.890 –0.810 –0.700 VILmin –1.990 –1.950 –1.925 VIHAmin –1.205 –1.105 –1.035 VILAmax –1.500 –1.475 –1.440 VIH –2.8 –2.8 –2.8 VILH –4.7 –4.7 –4.7 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VIH VIL Gnd 1,16 6 1,16 1,16 1,16 1,16 6 6 6 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 6 1,16 1,16 6 1,16 1,16 1,16 1,16 6 Characteristic Power Supply Drain Current Symbol ICC1 ICC2 Input Current IinH1 IinH2 IinH3 IinH4 Leakage Current IinL1 IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 3) IOS NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 5 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature –30°C 25°C 85°C Pin Under Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 9,10 9,10 9,10 9,10 9,10 9,10 9,10 VIHT –3.2 –3.2 –3.2 VILT –4.4 –4.4 –4.4 VEE –5.2 –5.2 –5.2 IL –0.25 –0.25 –0.25 mA IOL 16 16 16 IOH –0.40 –0.40 –0.40 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHT VILT VEE 8 8 8 8 8 8 8 8 8 8 8 8,15 8,11 8,12 8,13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Clock Input VIHmax VILmin 7 7 14 IL IOL IOH Gnd 1,16 6 1,16 1,16 1,16 1,16 6 6 6 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 6 1,16 1,16 6 1,16 1,16 1,16 1,16 6 Characteristic Power Supply Drain Current Symbol ICC1 ICC2 Input Current IinH1 IinH2 IinH3 IinH4 Leakage Current IinL1 IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 2) IOS NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 6 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.) Test Limits Pin Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 –65 3.880 3.880 3.405 3.405 –20 –65 3.900 3.900 2.4 3.070 3.070 3.385 3.385 0.94 3.980 3.980 3.430 3.430 –20 –65 4.110 4.110 –10 –10 –10 –10 –1.6 –1.6 1.7 1.7 0.7 –30°C Min –88 5.2 375 375 375 375 6.0 6.0 3.0 2.0 2.0 1.0 100 100 –10 –10 –10 –10 –1.6 –1.6 3.67 4.000 4.000 2.6 3.110 3.110 3.410 3.410 0.80 4.050 4.050 3.465 3.465 –20 Clock Input VIHmax VILmin 3.87 4.190 4.190 4.070 4.070 2.8 3.135 3.135 3.445 3.445 0.72 Vdc Vdc mAdc Vdc 4.300 4.300 Max Min –80 5.2 250 250 250 250 6.0 6.0 3.0 100 100 –10 –10 –10 –10 –1.6 –1.6 2.0 2.0 1.0 25°C Max Min –80 5.2 250 250 250 250 6.4 6.4 3.6 100 100 µAdc µAdc 85°C Max Unit mAdc mAdc µAdc Characteristic Power Supply Drain Current Symbol ICC1 ICC2 IinH1 Input Current IinH2 IinH3 IinH4 Leakage Current IinL1 mAdc IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 3) IOS mAdc Vdc Vdc NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. Page 7 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature –30°C 25°C 85°C Pin Under Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 5 4 4 5 11,12,13 11,12,13 4 11,12,13 11,12,13 5 11,12,13 11,12,13 11,12,13 11,12,13 7 Clock Input VIHmax VILmin 9,10 9,10 9,10 9,10 9 10 4 15 11 12 13 5 5 4 4 4 5 9 10 5 VIHmax 4.110 4.190 4.300 VILmin 3.070 3.110 3.135 VIHAmin 3.795 3.895 3.965 VILAmax 3.500 3.525 3.560 VIH 2.4 2.4 2.4 VILH 0.5 0.5 0.5 (VEE) Gnd 8 8 8 8 8 8 8 8 8 8 8 8,15 8,11 8,12 8,13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VIH VIL Characteristic Power Supply Drain Current Symbol ICC1 ICC2 Input Current IinH1 IinH2 IinH3 IinH4 Leakage Current IinL1 IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 3) IOS NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 8 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature –30°C 25°C 85°C Pin Under Under Test 8 6 15 11 12 13 4 5 5 9 10 15 11 12 13 9 10 14 2 3 7 2 3 7 2 3 2 3 7 9,10 9,10 9,10 9,10 9,10 9,10 9,10 VIHT 2.0 2.0 2.0 VILT 0.8 0.8 0.8 VCC 5.0 5.0 5.0 IL –0.25 –0.25 –0.25 mA IOL 16 16 16 IOH –0.40 –0.40 –0.40 (VEE) Gnd 8 8 8 8 8 8 8 8 8 8 8 8,15 8,11 8,12 8,13 8 8 14 8 8 8 7 8 8 8 7 8 8 8 8 8 8 Clock Input VIHmax VILmin TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHT VILT VCC 1,16 6 1,16 1,16 1,16 1,16 6 6 6 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 6 1,16 1,16 6 1,16 1,16 1,16 1,16 6 IL IOL IOH Characteristic Power Supply Drain Current Symbol ICC1 ICC2 Input Current IinH1 IinH2 IinH3 IinH4 Leakage Current IinL1 IinL2 Reference Voltage Logic ‘1’ Output Voltage VBB VOH1 (Note 1) VOH2 Logic ‘0’ Output Voltage VOL1 (Note 1) VOL2 Logic ‘1’ Threshold Voltage Logic ‘0’ Threshold Voltage Short Circuit Current VOHA (Note 2) VOLA (Note 3) IOS NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 9 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. SWITCHING CHARACTERISTICS ML12509, ML12511, ML12513 Pin Under Test 2 2 7 7 11 9 11 9 2 440 500 — — — — 480 550 — — — — 440 500 — — — — –30°C Min — — — — 5.0 5.0 5.0 5.0 Typ — — — — — — — — Max 8.1 7.5 8.4 6.5 — — — — Min — — — — 5.0 5.0 5.0 5.0 25°C Typ — — — — — — — — Max 8.1 7.5 8.1 6.5 — — — — Min — — — — 5.0 5.0 5.0 5.0 85°C Typ — — — — — — — — Max 8.9 82 8.9 7.1 — — — — Unit ns Pulse Gen.1 15 15 A A 15 15 15 15 TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW: Pulse Gen.2 — — — — * — * — Pulse Gen.3 — — — — — * — * VIHmin IHmin — — — — — — — — VILmin ILmin 11,12,13 11,12,13 — — * 11,12,13 * 11,12,13 VF –3.0 V 9,10 9,10 — — 9,10 * 9.10 * VEE –3.0 V 8 8 8 8 8 8 8 8 VCC +2.0 1,6,16 1,6,16 1,6,16 1,6,16 1,6,16 1,6,16 1,6,16 1,6,16 Characteristic Propagation Delay (See Figures 3 and 5) Symbol t15+ 2+ t15+ 2– t5+ 7+ t5– 7– tsetup1 tsetup2 trel1 trel2 fmax Setup Time (See Figures 4 and 5) Release Time (See Figures 4 and 5) Toggle Frequency (See Figure 6) ML12509 : 5/6 ML12511 : 8/9 ns ns ns ns MHz — — — — — — 11 11 — — — — 8 8 16 16 *Test inputs sequentially, with Pulse Generator 2 or 3 as indicated connected to input under test, and the voltage indicated applied to the other input(s) of the same type ( i.e., MECL or MTTL). –30°C VIHmin VILmin 1.03 0.175 25°C 1.115 0.200 85°C 1.20 0.235 Vdc Vdc Figure 3. AC Voltage Waveforms Pulse Generator 1 t++ Q (Pin 2) 50% 80% 50% 20% VIHmin VILmin t+ – Q (Pin 3) 50% + In MTTL Out 50% t++ t–– –1.5 V Figure 4. Setup and Release Time Waveforms Pulse 50 Generator % 1 tsetup1 Pulse Generator tsetup2 2 Pulse Generator +1.5 V 3 Q (Pin 2) 80% 20% 80% 50% 90% 10% Divide by 5 — ML12509 Divide by 8 — ML12511 Di id b 10 ML12513 20% VIHmin VILmin VIHmin VILmin 0V VEE Pulse Generator 1 Pulse 50% Generator t rel2 2 Pulse Generator 3 –1.5 V Q (Pin 2) 80% 20% VIHmin VILmin VIHmin VILmin 0V VEE 50% trel1 80% 20% 90% 10% Divide by 6 — ML12509 Divide by 9 — ML12511 Di id b 11 ML12513 Page 10 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 5. AC Test Circuit Vin VCC = 2.0 V Vout (Scope Channel B) 50 Pulse Generator #1 25 µF 1 6 16 0.1 µF Vout 100 Vin 13 12 E1 E2 E3 E4 E5 C Q 2 Pulse Generator #2 50 100 Vin 11 10 9 15 3 Q Vout 14 950 Pulse Generator #3 5 50 + VBB 1950 7 4 – MECL to MTTL Trans– lator 8 Vin (Scope Channel A) MC10109 or equiv. A All Pulse Generators are EH 137 or equiv. Pulse Generators 1 and 2: PRF = 10 MHz PW = 50% Duty Cycle t + = t – = 2.0 ± 0.2 ns Pulse Generator 3: PRF = 2.0 MHz PW = 50% Duty Cycle t + = t – = 5.0 ± 0.5 ns 0.1 µF VEE = –3.0 V CT 50 VEE = –3.0 V All resistors are +1%. All input and output cables to the scope are equal lengths of 50 Ω coaxial cable. The 1950 Ω resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe. CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance. Unused output connected to a 50 Ω resistor to ground. Page 11 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 6. Maximum Frequency Test Circuit VCC = 2.0 V 0.1 µF 5.0 µF Vout to Scope 1 16 13 E1 Vin (To Scope) VEE 11 E3 10 9 0.1 µF 15 C 1.0 k 14 VBB 0.1 µF 8 0.1 µF VEE = –3.0 V Unused output connected to a 50 Ω resistor to ground 12 E2 Q 2 E4 E5 Q 3 800 mV Clock Input DIVIDE BY 6 850 mV typ Q (Pin 2) 3 Cycles 3 Cycles DIVIDE BY 9 800 mV Clock Input 850 mV typ Q (Pin 2) 5 Cycles 4 Cycles Page 12 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 7. State Diagram DIVIDE BY 5/6 (ML12009/ML12509) Enable = 0 Q1 1 0 0 0 1 1 Q2 1 1 0 0 0 1 Q3 1 1 1 0 0 0 111 011 001 010 101 Enable = 1 110 100 000 Enable = 1 DIVIDE BY 8/9 (ML12011) 0101 0010 1000 1100 1010 Enable = 0 Q1 1 0 0 1 1 0 0 1 1 Q2 1 1 0 0 1 1 0 0 1 Q3 1 1 1 0 0 1 1 0 0 Q4 1 1 1 1 1 0 0 0 0 1110 0110 0000 0111 1111 Enable = 1 0001 1101 Enable = 1 1001 0011 1011 0100 APPLICATIONS INFORMATION The primary application of these devices is as a high–speed variable modulus prescaler in the divide by N section of a phase–locked loop synthesizer used as the local oscillator of two–way radios. Proper VHF termination techniques should be followed when the clock is separated from the prescaler by any appreciable distance. In their basic form, these devices will divide by 5/6 or 8/9. Division by 5, or 8 occurs when any one or all of the five gate inputs E1 through E5 are high. Division by 6, or 9 occurs when all inputs E1 through E5 are low. (Unconnected MTTL inputs are normally high, unconnected MECL inputs are normally low). With the addition of extra parts, many different division configurations may be obtained. Page 13 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS SO 16 = -5P PLASTIC PACKAGE (ML12009-5P, ML12011-5P) CASE 751B–05 (SO–16) ISSUE J –B– 1 8 –A– 16 9 P 8 PL 0.25 (0.010) M B S G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C –T– SEATING PLANE R X 45 M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R –A– 16 9 P DIP 16 = EP PLASTIC PACKAGE (ML12009EP, ML12011EP) CASE 648–08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 F S C L –T– H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 14 of 14 www.lansdale.com Issue A