ML12202D

ML12202 MECL PLL Components Serial Input PLL Frequency Synthesizer Legacy Device: Motorola MC12202 The ML12202 is a 1.1 GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse–swallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications. The technology is utilized allows for low power operation at a minimum supply voltage of 2.7 V The device is designed for . operation over 2.7 to 5.5 V supply range for input frequencies up to 1.1 GHz with a typical current drain of 6.5 mA. The low power consumption makes the ML12202 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 64/65 or 128/129 divide ratio. • Low Power Supply Current of 5.8 mA Typical for ICC and 0.7 mA Typical for IP • Supply Voltage of 2.7 to 5.5 V • Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or128/129 • On–Chip Reference Oscillator/Buffer • Programmable Reference Divider Consisting of a Binary 14–Bit Programmable Reference Counter • Programmable Divider Consisting of a Binary 7–Bit Swallow Counter and an 11–Bit Programmable Counter • Phase/Frequency Detector With Phase Conversion Function • Balanced Charge Pump Outputs • Dual Internal Charge Pumps for Bypassing the First Stage of the Loop Filter to Decrease Lock Time • Outputs for External Charge Pump • Operating Temperature Range of TA = –40 to 85°C NOTE: Also available is the ML12210, a 2.5 GHz version of this function. Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. Page 1 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. Page 2 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. Page 3 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. DATA ENTRY FORMAT The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable pin is HIGH or OPEN. Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider “L” = data is transferred into 18–bit latch of programmable divider WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect the VCO. PROGRAMMABLE REFERENCE DIVIDER 16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to 16383) and the prescaler divide ratio (SW = 0 for ÷128/129, SW = 1 for ÷64/65). An R divide ratio less than 8 is prohibited. Page 4 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. Page 5 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. PHASE CHARACTERISTICS/VCO CHARACTERISTICS The phase comparator in the ML12202 is a high speed digital phase frequency detector circuit. The circuit determines the “lead”or “lag” phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input. Since these edges occur only once per cycle, the detector has a range of ±2π radians. The phase comparator outputs are standard CMOS rail–to–rail levels (VP to GND for φP and VCC to GND for φR), designed for up to 20MHz operation into a 15pF load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics. The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are controlled by the FC pin. The polarity of the phase comparator outputs, φR and φP, as well as the charge pump output Do can be reversed by switching the FC pin. Page 6 of 11 www.lansdale.com Issue A ML12202 LANSDALE Semiconductor, Inc. For FC = HIGH: fr lags fp in phase OR fp>fr in frequency When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.The signal on φR indicates to the VCO to decrease in frequency to bring the loop into lock. fr leads fp in phase OR fpfr in frequency When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.The signal on φP indicates to the VCO to increase in frequency to bring the loop into lock. fr leads fp in phase OR fp