1024EA

ispLSI 1024EA ® In-System Programmable High Density PLD Features • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 48 I/O Pins, Two Dedicated Inputs — 144 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User Selectable 3.3V or 5V I/O Supports MixedVoltage Systems (VCCIO Pin) — Open-Drain Output Option • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram A0 DQ C7 Output Routing Pool 0139/1024EA Output Routing Pool A1 A2 A3 A4 A5 A6 A7 DQ DQ C6 Logic Array C5 DQ GLB C4 C3 C2 C1 Global Routing Pool (GRP) B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 CLK Description The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024EA features 5V in-system diagnostic capabilities via IEEE 1149.1 Test Access Port. The ispLSI 1024EA device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. A functional superset of the ispLSI 1024 architecture, the ispLSI 1024EA device adds user selectable 3.3V or 5V I/O and open-drain output options. The basic unit of logic on the ispLSI 1024EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (Figure 1). There are a total of 24 GLBs in the ispLSI 1024EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com June 2000 1024ea_01 1 Specifications ispLSI 1024EA Functional Block Diagram Figure 1. ispLSI 1024EA Functional Block Diagram RESET VCCIO Generic Logic Blocks (GLBs) GOE 1/IN 5 GOE 0/IN 4 C7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0 A1 C6 I/O 47 I/O 46 I/O 45 I/O 44 Output Routing Pool (ORP) C5 Output Routing Pool (ORP) A3 A4 A5 A6 Global Routing Pool (GRP) C4 C3 C2 C1 C0 lnput Bus lnput Bus A2 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 A7 B0 TDI TDO TMS TCK B1 B2 B3 B4 B5 B6 B7 Clock Distribution Network Megablock Output Routing Pool (ORP) Input Bus CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 The device also has 48 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pin to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V-compatible voltages. Eight GLBs, 16 I/O cells, dedicated inputs (if available) and one ORP are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1024EA device contains three Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1024EA device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI 1024EA device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 1024EA are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools. 2 Y0 Y1 Y2 Y3 0139B/1024EA Specifications ispLSI 1024EA Boundary Scan Figure 2. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp Tbtvo TDO Tbtcpsu Data to be captured Valid Data Tbtco Valid Data Tbtoz Tbtcph Data Captured Tbtuov Data to be driven out Tbtuco Valid Data Tbtuoz Valid Data Symbol tbtcp tbtch tbtcl tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov Parameter TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Min 100 50 50 20 25 50 – – – 40 25 – – – Max – – – – – – 25 25 25 – – 50 50 50 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 3 Specifications ispLSI 1024EA Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER Supply Voltage Supply Voltage: Output Drivers Input Low Voltage Input High Voltage Commercial 5V 3.3V TA = 0°C to + 70°C MIN. 4.75 4.75 3.0 0 2.0 MAX. 5.25 5.25 3.6 0.8 Vcc+1 UNITS V V V V V VCC VCCIO VIL VIH Table 2-0005/1024EA Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) Y0 Clock Capacitance TYPICAL 8 10 UNITS pf pf TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V Table 2-0006/1024EA C1 C2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM — UNITS Cycles Table 2-0008/1024EA 4 Specifications ispLSI 1024EA Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5ns 1.5V 1.5V See Figure 3 Table 2-0003/1024EA Figure 3. Test Load + 5V R1 Device Output R2 CL* Test Point Output Load Conditions (see Figure 3) TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470Ω ∞ 470Ω ∞ 470Ω R2 390Ω 390Ω 390Ω 390Ω 390Ω CL 35pF 35pF 35pF 5pF 5pF *CL includes Test Fixture and Probe Capacitance. 0213a C Table 2-0004/1024EA DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL = 8 mA IOH = -2 mA, VCCIO = 3.0V IOH = -4 mA, VCCIO = 4.75V 0V ≤ VIN ≤ VIL (Max.) (VCCIO - 0.2)V ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL VCCIO = 5.0V or 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz CONDITION MIN. — 2.4 2.4 — — — — — — TYP.3 — — — — — — — — 152 MAX. UNITS 0.4 — — -10 10 10 -200 -240 — V V V µA µA µA µA mA mA VOL VOH IIL IIH IIL-PU IOS1 ICC2, 4, 5 Table 2-0007/1024EA 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum ICC. 5 Specifications ispLSI 1024EA External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND. 4 #2 1 2 3 4 5 6 7 8 9 DESCRIPTION 1 -200 — — 200 1 tsu2 + tco1 -125 — — 125 100 167 4.5 — 0.0 5.5 — 0.0 — 5.0 — — — — 3.0 3.0 3.0 0.0 7.5 10.0 — — — — 4.5 — — 5.5 — 10.0 — 12.0 12.0 7.0 7.0 — — — — -100 — — 100 77 125 6.0 — 0.0 7.0 — 0.0 — 6.5 — — — — 4.0 4.0 3.5 0.0 10.0 12.5 — — — — 6.0 — — 7.0 — 13.5 — 15.0 15.0 9.0 9.0 — — — — MIN. MAX. MIN. MAX. MIN. MAX. 4.5 6.0 — — — — 3.5 — — 4.0 — 5.5 — 7.0 7.0 4.5 4.5 — — — — UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 1. 2. 3. 4. A A A — — — A — — — — A — B C B C — — — — Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle 3 Clock Frequency with External Feedback ( ) 143 250 3.0 — 0.0 3.5 — 0.0 — 3.5 — — — — 2.0 2.0 ( twh 1+ twl ) GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low 20 21 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. Table 2-0030A/1024EA v.2.5 6 Specifications ispLSI 1024EA Internal Timing Parameters1 PARAM. # 2 DESCRIPTION -200 -125 -100 MIN. MAX. MIN. MAX. MIN. MAX. — — 3.0 0.0 — — — — — — — — — — — — — — 0.2 1.0 — — — — 1.5 — — — 0.3 4.0 — — 4.0 4.0 1.1 1.3 1.5 1.7 2.1 2.5 1.7 1.8 1.9 1.9 1.9 0.6 — — 1.4 3.8 2.5 2.1 2.5 0.0 0.8 0.1 — — 3.0 0.0 — — — — — — — — — — — — — — 0.3 3.5 — — — — 2.8 — — — 0.3 4.0 — — 4.6 4.6 1.9 1.7 1.9 2.1 2.5 2.9 3.4 3.1 3.6 3.6 3.6 1.2 — — 1.4 4.9 3.8 5.7 3.9 0.3 1.3 0.2 — — 3.4 0.0 — — — — — — — — — — — — — — 1.4 4.0 — — — — 3.5 — — — 0.4 4.0 — — 5.0 5.0 2.2 2.1 2.3 2.5 2.9 3.3 4.9 3.8 4.3 4.3 4.3 2.1 — — 1.7 5.0 4.5 7.2 4.7 0.3 1.4 0.4 UNITS Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP 22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 24 GLB Loads 34 4 ProductTerm Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered) 36 1 ProductTerm/XOR Path Delay 37 20 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tgrp1 tgrp4 tgrp8 tgrp16 tgrp24 GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck tgfb ORP 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay 46 GLB Product Term Clock Delay 47 GLB Feedback Delay 48 ORP Delay 49 ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. torp torpbp Table 2-0036A/1024EA v.2.5 7 Specifications ispLSI 1024EA Internal Timing Parameters1 PARAM. # DESCRIPTION -200 -125 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. — — — — — 0.9 0.9 0.8 0.0 0.8 — 0.9 5.0 3.1 3.1 1.4 0.9 0.9 1.8 0.0 2.8 0.0 — — — — — 1.1 0.9 0.8 0.0 0.8 — 1.7 5.0 4.0 4.0 3.0 1.1 0.9 1.8 0.0 2.8 2.1 — — — — — 1.9 1.5 0.8 0.0 0.8 — 2.0 5.0 5.1 5.1 3.9 1.9 1.5 1.8 0.0 2.8 5.1 Outputs tob tsl toen todis tgoe Clocks 50 Output Buffer Delay 51 Output Buffer Delay, Slew Limited Adder 52 I/O Cell OE to Output Enabled 53 I/O Cell OE to Output Disabled 54 Global OE 55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) 56 Clock Delay, Y1 or Y2 to Global GLB Clock Line 57 Clock Delay, Clock GLB to Global GLB Clock Line 58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 59 Clock Delay, Clock GLB to I/O Cell Global Clock Line 60 Global Reset to GLB and I/O Registers ns ns ns ns ns ns ns ns ns ns ns tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr Global Reset 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1024EA v.2.5 8 Specifications ispLSI 1024EA ispLSI 1024EA Timing Model I/O Cell GRP #47 Ded. In GLB Feedback #34 GRP4 #30 GRP Loading Delay #29, 31 - 33 Comb 4 PT Bypass GLB Reg Bypass #39 GLB Reg Delay D RST Reset #60 #40 - 43 Q ORP Bypass #49 ORP Delay #48 #50, 51 I/O Pin (Output) ORP I/O Cell #28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27 I/O Pin (Input) Reg 4 PT Bypass #35 20 PT XOR Delays #36 - 38 #52, 53 #60 Clock Distribution Y1,2,3 #56 - 59 Control RE PTs OE #44 - 46 CK 0491/1032EA Y0 GOE 0,1 #55 #54 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 0.6 = = = = 1.6 = = = = 7.4 = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.5) Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#48 + #50) (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9) th tco Derivations of tsu, th and tco from the Clock GLB 1 tsu = = = 0.8 = = = = 1.4 = = = = 7.2 = Logic + Reg (setup) - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#55 + #42 + #57) (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8) Clock (max) + Reg (hold) - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#55 + #42 + #57) + (#41) - (#22 + #30 + #37) (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9) Clock (max) + Reg (clock-to-out) + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#55 + #42 + #57) + (#42) + (#48 + #50) (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9) th tco 1. Calculations are based upon timing specifications for the ispLSI 1024EA-200. Table 2-0042a/1024EA v.2.5 9 Specifications ispLSI 1024EA Maximum GRP Delay vs GLB Loads 4 ispLSI 1024EA-100 GRP Delay (ns) 3 ispLSI 1024EA-125 ispLSI 1024EA-200 2 1 1 4 8 16 24 GRP/GLB/1024EA GLB Load Power Consumption Power consumption in the ispLSI 1024EA device depends on two primary factors: the speed at which the device is operating, and the number of product terms Figure 4. Typical Device Power Consumption vs fmax 260 240 220 ICC (mA) used. Figure 4 shows the relationship between power and operating speed. ispLSI 1024EA 200 180 160 140 120 100 0 50 100 150 fmax (MHz) 200 250 Notes: Configuration of eight 16-bit counters Typical current at 5V, 25°C Icc can be estimated for the ispLSI 1024EA using the following equation: Icc = 17mA + (# of PTs * .726) + (# of nets * Max Freq * .0043) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating conditions and the program in the device, the actual Icc should be verified. 0127/1024EA 10 Specifications ispLSI 1024EA Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 GOE 0/IN 41 GOE 1/IN 51 TDI TMS TDO TCK RESET Y0 Y1 TQFP PIN NUMBERS 19, 23, 31, 42, 46, 54, 69, 73, 81, 92, 96, 4, 91 8 18 68 35 58 17 9 67 20, 28, 32, 43, 47, 55, 70, 78, 82, 93, 97, 5, 21, 29, 33, 44, 48, 56, 71, 79, 83, 94, 98, 6, 22, 30, 34, 45, 53, 57, 72, 80, 84, 95, 3, 7 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Input - Functions as an input pin to load programming data into the device and also used as one of the two control pins for the ispJTAG state machine. Input - Controls the operation of the ISP state machine. Output - Functions as an output pin to read serial shift register data. Input - Functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. 15, 62, 11, 66, 36, 37, 89, 90 40, 41, 85, 86 Ground (GND) Vcc Supply voltage for output drivers, 5V or 3.3V. 2, 25, 39, 52, 75, 88, 12, 26, 49, 63, 76, 99, 13, No Connect 27, 50, 64, 77, 100 Table 2-0002A/1024EA Y2 60 Y3 59 GND VCC VCCIO NC2 14, 61, 10, 65, 16 1, 24, 38, 51, 74, 87, 1. Pins have dual function capability which is software selectable. 2. NC pins are not to be connected to any active signals, Vcc or GND. 11 Specifications ispLSI 1024EA Pin Configurations ispLSI 1024EA 100-Pin TQFP Pinout Diagram NC2 NC2 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GOE 0/IN 41 GND GND NC2 NC2 VCC VCC I/O 35 I/O 34 I/O 33 I/O 32 I/O 31 I/O 30 I/O 29 NC2 NC2 2NC 2NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 1GOE 1/IN 5 Y0 VCC VCC 2NC 2NC GND GND VCCIO RESET TDI I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 2NC 2NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ispLSI 1024EA Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC2 NC2 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 TMS Y1 VCC VCC NC2 NC2 GND GND Y2 Y3 TCK I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 NC2 NC2 1. Pins have dual function capability which is software selectable. 2. NC pins are not to be connected to any active signal, VCC or GND. 100-TQFP/1024EA I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 TDO GND GND 2NC 2NC VCC VCC I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 2NC 2NC 2NC 2NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 12 Specifications ispLSI 1024EA Part Number Description ispLSI 1024EA - XXX Device Family X XXXX X Grade Blank = Commercial Package T100 = 100-Pin TQFP Power L = Low 0212/1024EA Device Number Speed 200 = 200 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax ispLSI 1024EA Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) 200 125 100 tpd (ns) 4.5 7.5 10 ORDERING NUMBER ispLSI 1024EA-200LT100 ispLSI 1024EA-125LT100 ispLSI 1024EA-100LT100 PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Table 2-0041A/1024EA 13