2128E

ispLSI 2128E In-System Programmable SuperFAST™ High Density PLD Features • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 I/O Pins, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional/JEDEC Upward Compatible with ispLSI 2128 Devices • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems — PCI Compatible Outputs — Open-Drain Output Option — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms 2 ® ® Functional Block Diagram Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 C7 Output Routing Pool (ORP) A0 A1 C6 A2 D Q C5 A3 D Q C4 Output Routing Pool (ORP) A4 D Q GLB C3 A5 D Q C2 A6 C1 A7 B0 B1 Global Routing Pool (GRP) B2 B3 B4 B5 B6 B7 C0 Output Routing Pool (ORP) Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 0139(9A)/2128 Description The ispLSI 2128E is a High Density Programmable Logic Device. The device contains 128 Registers, 128 Universal I/O pins, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2128E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2128E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 128 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com November 1998 2128e_02 1 Output Routing Pool (ORP) Logic Array Output Routing Pool (ORP) Specifications ispLSI 2128E Functional Block Diagram Figure 1. ispLSI 2128E Functional Block Diagram RESET GOE 0 GOE 1 Input Bus Output Routing Pool (ORP) Megablock Generic Logic Blocks (GLBs) Output Routing Pool (ORP) D4 D3 D2 D1 D0 IN 5 IN 4 C7 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 D7 D6 D5 TDI/IN 7 TDO/IN 6 C6 C5 C4 I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 TCK/ IN 0 TMS/IN 1 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 A0 A1 A2 A3 Input Bus A4 Output Routing Pool (ORP) C2 A5 C1 A6 C0 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool (ORP) Input Bus BSCAN Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 Output Routing Pool (ORP) 0139/2128E Global Routing Pool (GRP) Output Routing Pool (ORP) Input Bus C3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 2 IN 3 individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2128E device contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128E are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools. 2 Y0 Y1 Y2 Specifications ispLSI 2128E Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER Supply Voltage: Logic Core, Input Buffers Supply Voltage: Output Drivers Input Low Voltage Input High Voltage 5V 3.3V TA = 0°C to +70°C MIN. 4.75 4.75 3.0 0 2.0 MAX. 5.25 5.25 3.6 0.8 Vcc+1 UNITS V V V V V Table 2-0005/2128E VCC VCCIO VIL VIH Capacitance (TA=25°C, f=1.0 MHz) SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYP 8 8 10 UNITS pf pf pf TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V Table 2-0006/2128E C1 C2 C3 Erase/Reprogram Specification PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM – UNITS Cycles Table 2-0008/2128E 3 Specifications ispLSI 2128E Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 1.5V 1.5V See Figure 2 Table 2-0003/2128E Figure 2. Test Load + 5V R1 Device Output Test Point R2 CL* Output Load Conditions (see Figure 2) TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470Ω ∞ 470Ω ∞ 470Ω R2 390Ω 390Ω 390Ω 390Ω 390Ω CL 35pF 35pF 35pF 5pF 5pF *CL includes Test Fixture and Probe Capacitance. 0213A C Table 2 - 0004A/2000 DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL = 8 mA IOH = -4 mA 0V ≤ VIN ≤ VIL (Max.) (VCCIO - 0.2)V ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ 2.0V VCCIO = 5.0V or 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz CONDITION MIN. – 2.4 – – – -10 – – TYP.3 – – – – – – – 165 MAX. UNITS 0.4 – -10 10 10 -250 -240 – V V µA µA µA µA mA mA VOL VOH IIL IIH IIL-PU IOS1 ICC3,4 Table 2-0007/2128E 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Meaured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 4 Specifications ispLSI 2128E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 2 4# COND. A A A – – – A – – – – A – B C B C – – DESCRIPTION1 -180 – – 180 1 tsu2 + tco1 -135 – – 135 100 143 5.0 – 0.0 6.0 – 0.0 – 5.0 – – – – 3.5 3.5 7.5 10.0 – – – – 4.0 – – 4.5 – 10.0 – 12.0 12.0 7.0 7.0 – – – – -100 10.0 13.0 – – – – 5.0 – – 6.0 – 13.5 – 15.0 15.0 9.0 9.0 – – MIN. MAX. MIN. MAX. MIN. MAX. 5.0 7.5 – – – – 3.0 – – 3.5 – 7.0 – 10.0 10.0 5.0 5.0 – – UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl 1. 2. 3. 4. 1 Data Prop Delay, 4PT Bypass, ORP Bypass 2 Data Prop Delay 3 Clk Freq with Internal Feedback3 4 Clk Freq with External Feedback ( 5 Clk Frequency, Max. Toggle 6 GLB Reg Setup Time before Clk, 4 PT Bypass 7 GLB Reg Clk to Output Delay, ORP Bypass 8 GLB Reg Hold Time after Clk, 4 PT Bypass 9 GLB Reg Setup Time before Clk 10 GLB Reg Clk to Output Delay 11 GLB Reg Hold Time after Clk 12 External Reset Pin to Output Delay 13 External Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synch Clk Pulse Duration, High 19 External Synch Clk Pulse Duration, Low 100 77.0 100 6.5 – 0.0 8.0 – 0.0 – 6.5 – – – – 5.0 5.0 ) 125 200 4.0 – 0.0 5.0 – 0.0 – 4.0 – – – – 2.5 2.5 Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. Table 2-0030A/2128E 5 Specifications ispLSI 2128E Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER Inputs # 2 DESCRIPTION -180 -135 -100 MIN. MAX. MIN. MAX. MIN. MAX. – – – – – – – – – 0.7 3.3 – – – – 1.0 – – – – – – – 0.7 0.9 – 0.5 1.1 0.6 1.9 2.9 3.9 3.9 3.9 0.0 – – 0.3 0.6 4.8 5.9 4.0 0.9 0.4 1.6 1.5 3.0 3.0 2.0 0.7 0.9 4.4 – – – – – – – – – 0.7 4.3 – – – – 2.5 – – – – – – – 1.6 1.8 – 0.5 1.7 1.2 3.7 4.2 5.2 5.2 5.2 0.5 – – 0.3 1.1 6.0 6.9 5.5 1.0 0.5 1.6 1.5 3.4 3.4 3.6 1.6 1.8 6.3 – – – – – – – – – 1.2 4.0 – – – – 4.1 – – – – – – – 2.7 2.7 – 0.5 2.2 1.7 5.8 5.8 6.8 7.3 8.0 0.5 – – 0.3 1.3 6.1 8.6 7.1 1.4 0.4 1.6 10.0 4.2 4.2 4.8 2.7 2.7 9.2 UNITS tio tdin GRP 20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tgrp GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 Global Reset tgr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/2128E 6 Specifications ispLSI 2128E ispLSI 2128E Timing Model I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25 - 27 Reset #45 D RST #29 - 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, #39 GLB ORP I/O Cell #21 I/O Delay #20 I/O Pin (Input) I/O Pin (Output) Control RE PTs OE #33 - 35 CK #43, 44 #42 #40, 41 Y0,1,2 GOE0, 1 0491/2128E Derivations of tsu, th and tco from the Product Term Clock tsu = = = 3.6 = = = = 3.4 = = = = 7.9 = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 0.6) Table 2-0042/2128E th tco Note: Calculations are based upon timing specifications for the ispLSI 2128E-180L. 7 Specifications ispLSI 2128E Power Consumption Power consumption in the ispLSI 2128E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax Figure 3 shows the relationship between power and operating speed. 500 450 400 ispLSI 2128E ICC (mA) 350 300 250 200 150 100 0 20 40 60 80 100 120 140 160 180 fmax (MHz) Notes: Configuration of eight 16-bit counters Typical current at 5V, 25° C ICC can be estimated for the ispLSI 2128E using the following equation: ICC = 27 + (# of PTs * 0.55) + (# of nets * max freq * 0.0058) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/2128E 8 Specifications ispLSI 2128E Pin Description NAME I/O 0 - I/O 4 I/O 5 - I/O 9 I/O 10 - I/O 14 I/O 15 - I/O 19 I/O 20 - I/O 24 I/O 25 - I/O 29 I/O 30 - I/O 34 I/O 35 - I/O 39 I/O 40 - I/O 44 I/O 45 - I/O 49 I/O 50 - I/O 54 I/O 55 - I/O 59 I/O 60 - I/O 64 I/O 65 - I/O 69 I/O 70 - I/O 74 I/O 75 - I/O 79 I/O 80 - I/O 84 I/O 85 - I/O 89 I/O 90 - I/O 94 I/O 95 - I/O 99 I/O 100 - I/O 104 I/O 105 - I/O 109 I/O 110 - I/O 114 I/O 115 - I/O 119 I/O 120 - I/O 124 I/O 125 - I/O 127 IN 2 - IN 5 GOE 0, GOE 1 RESET Y0, Y1, Y2 BSCAN TDI/IN 71 TQFP PIN NUMBERS 27, 35, 41, 46, 52, 59, 65, 71, 77, 83, 90, 95, 102, 116, 124, 130, 135, 141, 148, 154, 160, 167, 173, 3, 8, 16, 28, 36, 42, 47, 53, 60, 66, 72, 79, 85, 91, 96, 103, 119, 125, 131, 136, 143, 149, 155, 161, 168, 174, 4, 9, 17, 31, 37, 43, 48, 55, 61, 67, 73, 80, 86, 92, 97, 104, 120, 126, 132, 138, 145, 150, 156, 163, 169, 175, 5, 12, 18 32, 38, 44, 50, 57, 62, 68, 75, 81, 87, 93, 99, 105, 121, 127, 133, 139, 146, 151, 158, 164, 170, 176, 6, 14, DESCRIPTION 33, Input/Output Pins - These are the general purpose I/O pins used by the logic array. 39, 45, 51, 58, 63, 70, 76, 82, 88, 94, 101, 115, 123, 129, 134, 140, 147, 153, 159, 165, 171, 2, 7, 15, Dedicated input pins to the device. Global Output Enable input pins. Active Low (0) Reset pin which resets all of the GLB registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK options become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the ISP state machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as pin to control the operation of the programming state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as the pin to read the isp data. When BSCAN is high, it functions as a dedicated input pin. 106, 107, 112, 113 110, 109, 22 19, 21, 111 23 24 TCK/IN 01 TMS/IN 11 25 26 TDO/IN 61 GND 114 1, 64, 117, 172 13, 122, 10, 118, 20 11, 29, 40, 49, Ground (GND) 69, 84, 89, 108, 128, 137, 152, 157, 34, 144, 30, 142, 56, 78, 166 54, 74, 162 100, VCC 98, Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the same voltage level. No Connect Table 2-0002/2128E VCC VCCIO NC 1. Pins have dual function capability. 9 Specifications ispLSI 2128E Pin Configuration ispLSI 2128E 176-Pin TQFP Pinout Diagram I/O 113 I/O 112 I/O 111 I/O 110 GND I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 VCC I/O 104 I/O 103 I/O 102 VCCIO I/O 101 I/O 100 I/O 99 I/O 98 GND I/O 97 I/O 96 I/O 95 I/O 94 GND I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 VCC I/O 86 VCCIO I/O 85 I/O 84 I/O 83 I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 GND I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 VCCIO GND I/O 122 VCC I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 Y0 1NC Y1 RESET BSCAN 2 TDI/IN 7 2TCK/IN 0 2TMS/IN 1 I/O 0 I/O 1 GND VCCIO I/O 2 I/O 3 I/O 4 VCC I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 GND I/O 10 I/O 11 I/O 12 I/O 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ispLSI 2128E Top View 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 I/O 77 I/O 76 I/O 75 I/O 74 GND I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 VCC I/O 68 I/O 67 I/O 66 VCCIO GND I/O 65 I/O 64 TDO/IN 62 IN 5 IN 4 Y2 GOE 0 GOE 1 GND IN 3 IN 2 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 VCC I/O 58 VCCIO I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 GND I/O 14 I/O 15 I/O 16 I/O 17 GND I/O 18 I/O 19 I/O 20 I/O 21 VCCIO I/O 22 VCC I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 GND I/O 30 I/O 31 I/O 32 I/O 33 GND I/O 34 I/O 35 I/O 36 I/O 37 VCCIO I/O 38 I/O 39 I/O 40 VCC I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 GND I/O 46 I/O 47 I/O 48 I/O 49 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 176-TQFP/2128E 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 10 Specifications ispLSI 2128E Part Number Description ispLSI 2128E – XXX X XXXX X Device Family Device Number Speed 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Grade Blank = Commercial Package T176 = TQFP Power L = Low 0212/2128E ispLSI 2128E Ordering Information FAMILY ispLSI fmax (MHz) 180 135 100 tpd (ns) 5.0 7.5 10.0 ORDERING NUMBER ispLSI 2128E-180LT176 ispLSI 2128E-135LT176 ispLSI 2128E-100LT176 PACKAGE 176-Pin TQFP 176-Pin TQFP 176-Pin TQFP Table 2-0041/2128E 11