2D-FIR-E3-UT1

2D FIR Filter IP Core User’s Guide January 2011 IPUG89_01.0 Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 6 Chapter 2. Functional Description ........................................................................................................ 7 Key Concepts........................................................................................................................................................ 7 Block Diagram....................................................................................................................................................... 7 Coefficients ........................................................................................................................................................... 8 Interpolation and Decimation ....................................................................................................................... 8 Coefficient Generation ............................................................................................................................... 10 Dynamic Zoom and Pan...................................................................................................................................... 12 Primary I/O .......................................................................................................................................................... 13 Interface Descriptions ......................................................................................................................................... 13 Video Input/Output ..................................................................................................................................... 13 Coefficient Update...................................................................................................................................... 13 Chapter 3. Parameter Settings ............................................................................................................ 14 Architecture Tab.................................................................................................................................................. 14 Filter Specifications .................................................................................................................................... 15 Interpolation/Decimation Factors ............................................................................................................... 16 Active Region ............................................................................................................................................. 16 Edge Mode................................................................................................................................................. 16 Coefficients Specifications ......................................................................................................................... 16 Throughput................................................................................................................................................. 16 I/O Specification Tab........................................................................................................................................... 17 Input data ................................................................................................................................................... 17 Coefficients ................................................................................................................................................ 17 Vertical Filter Output .................................................................................................................................. 17 Output ........................................................................................................................................................ 17 Precision Control........................................................................................................................................ 18 Implementation Tab ............................................................................................................................................ 18 Memory Type ............................................................................................................................................. 18 Chapter 4. IP Core Generation............................................................................................................. 19 Licensing the IP Core.......................................................................................................................................... 19 Getting Started .................................................................................................................................................... 19 IPexpress-Created Files and Top Level Directory Structure............................................................................... 21 Instantiating the Core .......................................................................................................................................... 23 Running Functional Simulation ........................................................................................................................... 23 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 23 Hardware Evaluation........................................................................................................................................... 24 Enabling Hardware Evaluation in Diamond................................................................................................ 24 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 24 Updating/Regenerating the IP Core .................................................................................................................... 24 Regenerating an IP Core in Diamond ........................................................................................................ 24 Regenerating an IP Core in ispLEVER ...................................................................................................... 25 Chapter 5. Support Resources ............................................................................................................ 26 Lattice Technical Support.................................................................................................................................... 26 Online Forums............................................................................................................................................ 26 Telephone Support Hotline ........................................................................................................................ 26 E-mail Support ........................................................................................................................................... 26 Local Support ............................................................................................................................................. 26 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG89_1.0, January 2011 2 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Table of Contents Internet ....................................................................................................................................................... 26 References.......................................................................................................................................................... 26 LatticeECP2/M ........................................................................................................................................... 26 LatticeECP3 ............................................................................................................................................... 26 LatticeXP2.................................................................................................................................................. 26 Revision History .................................................................................................................................................. 26 Appendix A. Resource Utilization ....................................................................................................... 27 LatticeECP2 Devices .......................................................................................................................................... 27 Ordering Part Number................................................................................................................................ 27 LatticeECP2M Devices ....................................................................................................................................... 28 Ordering Part Number................................................................................................................................ 28 LatticeECP3 Devices .......................................................................................................................................... 28 Ordering Part Number................................................................................................................................ 28 LatticeXP2 Devices ............................................................................................................................................. 29 Ordering Part Number................................................................................................................................ 29 IPUG89_1.0, January 2011 3 2D FIR Filter IP Core User’s Guide Chapter 1: Introduction The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory. Its flexible architecture supports a wide variety of filtering operations on LatticeECP2™, LatticeECP2M™, LatticeECP3™ and LatticeXP2™ devices. The highly parameterized design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in system via a simple memory interface. Quick Facts Table 1-1 through Table 1-4 give quick facts about the 2D FIR Filter IP core for LattceECP2, LatticeECP2M, LatticeECP3, and LatticeXP2 devices. Table 1-1. 2D FIR Filter Quick Facts for LatticeECP2     Core Requirements 2D FIR IP configurations 5x5 single-rate, 704x480, CIRCULAR, non-separable FPGA Family Support LatticeECP2 Minimal Device Needed LFE2-6E-5T144C Target device LFE2-50E-6F484C Data Path Width Resource Utilization 8 LUTs 2000 sysMEM EBRs Registers 680 3 3 920 460 2 410 ® Lattice Implementation Lattice Diamond™ 1.1 or ispLEVER 8.1SP1 Synopsys® Synplify™ Pro for D-2010.03L-SP1 Synthesis Aldec® Active-HDL® 8.2 Lattice Edition Simulation IPUG89_1.0, January 2011 580 2 sysDSP Blocks Design Tool Support 5x5 single-rate, 704x480, XANDY, separable 5x5 single-rate, 704x480, None, separable Mentor Graphics® ModelSim® SE 6.3F 4 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Introduction Table 1-2. 2D FIR Filter Quick Facts for LatticeECP2M 2D FIR IP configurations 5x5 single-rate, 704x480, CIRCULAR, non-separable Core Requirements FPGA Family Support LFE2M20E-5F256C Target device LFE2M50E-6F484C 8 LUTs 2000 580 sysMEM EBRs 680 2 sysDSP Blocks Registers Design Tool Support 5x5 single-rate, 704x480, XANDY, separable LatticeECP2M Minimal Device Needed Data Path Width Resource Utilization 5x5 single-rate, 704x480, None, separable 3 3 2 920 460 410 Lattice Implementation Lattice Diamond 1.1 or ispLEVER 8.1SP1 Synthesis Synopsys Synplify Pro for D-2010.03L-SP1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor Graphics ModelSim SE 6.3F Table 1-3. 2D FIR Filter Quick Facts for LatticeECP3 2D FIR IP configurations 5x5 single-rate, 704x480, CIRCULAR, non-separable Core Requirements FPGA Family Support LFE3-17EA-6FTN256CES LFE3-17EA-7FN484C Data Path Width 8 LUTs 2160 sysMEM EBRs 630 Registers 3 3 2 930 460 410 Lattice Implementation Lattice Diamond 1.1 or ispLEVER 8.1SP1 Synthesis Synopsys Synplify Pro for D-2010.03L-SP1 Aldec Active-HDL 8.2 Lattice Edition Simulation IPUG89_1.0, January 2011 630 2 sysDSP Blocks Design Tool Support 5x5 single-rate, 704x480, XANDY, separable LatticeECP3 Minimal Device Needed Target device Resource Utilization 5x5 single-rate, 704x480, None, separable Mentor Graphics ModelSim SE 6.3F 5 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Introduction Table 1-4. 2D FIR Filter Quick Facts for LatticeXP2   2D FIR IP configurations 5x5 single-rate, 704x480, CIRCULAR, non-separable Core Requirements FPGA Family Support Minimal Device Needed LFXP2-5E-5M132C Target device LFXP2-40E-6F484C 8 LUTs 2000 580 sysMEM EBRs 680 2 sysDSP Blocks Registers Design Tool Support 5x5 single-rate, 704x480, XANDY, separable LatticeXP2 Data Path Width Resource Utilization 5x5 single-rate, 704x480, None, separable 3 2 2 920 460 410 Lattice Implementation Lattice Diamond 1.1 or ispLEVER 8.1SP1 Synthesis Synopsys Synplify Pro for D-2010.03L-SP1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor Graphics ModelSim SE 6.3F Features • Single color plane • Single-rate, interpolating, and decimating filter configurations • Input frame size set at compile-time • Static or dynamic zoom and pan • User-specified 2D convolution kernel • Separable and non-separable kernel support • Kernel symmetry optimization • Updatable coefficients IPUG89_1.0, January 2011 6 2D FIR Filter IP Core User’s Guide Chapter 2: Functional Description Key Concepts Two-dimensional video filtering is the process of producing pixels in an output frame using the values of pixels in an input frame by calculating each new pixel value as a weighted sum of nearby original pixel values. The number of original pixel values and their weights depends on the filtering algorithm employed. The set of weights is referred to as the “filter kernel” or “coefficient set”. Coefficient values depend on the type of filtering operation required. Interpolating filters insert new pixels in between the pixels in the incoming frame and calculate their values using original pixel values. In general, including more original pixels in the calculation results in a higher quality result, but requires more FPGA resources. Conversely, decimating filters drop unneeded input pixels. Output pixel values are calculated using all the original pixel values in the convolution window. The Lattice 2D FIR Filter IP core allows different interpolation and decimation factors for the horizontal and vertical dimensions. Block Diagram The high-level architecture of the 2D FIR Filter IP core is shown in Figure 2-1. Figure 2-1. 2D FIR Filter IP Core Block Diagram dvalid_in frmsync_in din[ ] ready Windowing Logic Line Buffers coeffwrite coeffaddr[ ] coeffwdat[ ] Coefficient Logic Up/Down Sampler actregion upleft decim_in Windowing Function Multiply-Add Saturation/ Rounding Arithmetic Unit dvalid_out frmsync_out dout[ ] Input data is stored in line buffers, then passed to windowing logic for edge mode handling and data alignment. Next, the up/down sampler decides which pixels, new and existing, will appear in the output frame, and fetches the appropriate coefficients from memory (more details in the section “Coefficients” on page 8). Optional control inputs allow real-time specification of the portion of the input frame used to generate output pixels (referred to as the “active region”), as well the down-sampling (decimation) factor. Coefficient values may also be updated dynamically. The combination of updatable active region, decimation factor, and coefficient values provides dynamic zoom and pan capability. Windowed data and coefficients are sent to the arithmetic unit, which multiplies the data values by their corresponding coefficients and sums the multiplication results. Depending on the configuration of the core, the multiplyadd operations may be distributed over several clock cycles, saving arithmetic resources. IPUG89_1.0, January 2011 7 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description Coefficients The 2D-FIR Filter works by walking a window of fixed size (specified at compile time) through the incoming video frame, illustrated in Figure 2-2. Figure 2-2. Windowing Function frame 0 01 0 02 0 03 0 04 0 00 1 11 1 12 1 13 1 14 1 10 2 21 2 22 2 23 2 24 2 20 frame 3 31 3 32 3 33 3 34 3 30 4 41 4 42 4 43 4 44 4 40 dat4 dat4 … dat4 … dat1 … dat1 dout [ WWIDTH*WHEIGHT*DWIDTH -1] dat0 … dat0 dat0 dout [ 0 ] Each pixel value is multiplied by a corresponding coefficient. The memory location of the coefficient for a given pixel is determined by the window dimensions, the interpolation or decimation values, and, perhaps, the symmetry and separability of the coefficient set, as well as the minimum interval between input samples. Interpolation and Decimation Interpolation is the process of expanding the size of an image by inserting new pixels between existing ones and calculating their values using the values of nearby existing pixels. The concept is illustrated in Figure 2-3. IPUG89_1.0, January 2011 8 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description Figure 2-3. Interpolation Example Existing image pixels New pixels Current output pixel Pixels in filter window In the example illustrated in Figure 2-3, nine output pixels are generated for every input pixel (the interpolation factor is 3). The example 5-by-5 filter window would normally require 25 multiply-accumulate operations to compute the value of a single output pixel, but because there are only four existing pixels in the window, only four multiplyaccumulates are needed. The windowing module, then, outputs the four values needed for calculating a particular output pixel, along with their corresponding filter coefficient values. The subset of the kernel coefficients needed is dependent on the position, or phase, of the output pixel, making this a “polyphase” interpolator. All coefficients for each phase of a polyphase interpolator occupy a single row in coefficient memory. For the configuration illustrated, there will be nine coefficient memory rows, each with four coefficient values. The coefficient address is the concatenation of the row and column addresses. Decimation is the inverse operation. All input pixel values are shifted into the windowing module’s line buffers, but output data and coefficient values are generated only every DECIMY rows and DECIMX columns. For decimating filters, optimization is possible in the follow-on arithmetic units, since processing is allowed to span multiple clock cycles. The number of clock cycles available for processing is DECIMY*DECIMX. The coefficients for each clock cycle occupy a single memory row. A scaler down-sampling by 3 in both X and Y will have 9 rows of coefficient memory. A further optimization is possible for decimating filters using the MULTICYCLE parameter, configured in the IPexpress™ GUI by the “Minimum input interval” setting. Setting this value to the minimum number of clock cycles between input pixel values allows the output pixel calculation to be spread over more clock cycles, further reducing arithmetic resource requirements. The number of clock cycles available for filter calculations is DECIMY*DECIMX*MULTICYCLE, and the coefficient memory will have that number of memory rows. IPUG89_1.0, January 2011 9 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description Coefficient Generation The coeffgen.tcl script in the $ip_install/scripts directory will map a coefficient set to appropriate memory locations based on a number of input parameters. Two files are needed: a parameter file and a coefficient file. The format for the parameter file is as follows: windowwidth=5 windowheight=5 separable=0 symmetry=0 x_eq_y=0 interpx=2 interpy=2 decimxmin=1 decimymin=1 multicycle=1 coefffile=path_to_coefficient_file coefftype=Floating point ctype=UNSIGNED cwidth=8 cpoints=8 filter_type=GAUSSIAN param=1.5 windowwidth and windowheight define the window dimensions. separable is 1 for separable kernels, 0 otherwise. symmetry values are: 0 for NONE; 1 for XONLY; 2 for YONLY; 3 for XANDY. interpx and interpy are the horizontal and vertical interpolation factors (1 means no interpolation). decimxmin and decimymin are the minimum decimation factors (for dynamically alterable decimation factors, the minimum values determine the memory mapping; for fixed decimation, these are simply the decimation values). multicycle is the minimum number of clock cycles between input pixels.coefffile is the path to the coefficient input file. coefftype is the data type of the coefficients in the input file (currently, only Floating point is supported). ctype is SIGNED or UNSIGNED. cwidth is the number of bits in the output coefficients. cpoints is the number of bits to the right of the binary point in the output coefficients. filter_type may be either CUSTOM, GAUSSIAN, LANCZOS, or BICUBIC. CUSTOM means the values are read from an input file; otherwise, they are generated by the script. The meaning of param depends on the filter type. The meaning of param depends on the filter type, as discussed below: • GAUSSIAN kernel values (in each dimension) are calculated as follows: X2 – --------2 2 e G  x  = ------------2 2 • LANCZOS kernel values (in each dimension) are calculated as follows: L  x  = sinc  x sinc  x  a  • BICUBIC kernel values are set as follows: a + 2 x 3 – a + 3 x 2 + 1  W  x  =  a x 3 – 5a x 2 + 8a x – 4a  0 for x  1 for 1  x  2 otherwise The parameter param sets the value of a. Common values are -.5 and -.75. IPUG89_1.0, January 2011 10 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description For custom coefficient sets, the input coefficient file is specified using a coefficients file. The coefficients file is a text file with one coefficient per line. Also,the coefficient sets file must contain all the coefficients, even if the coefficient sets is symmetric. For non-separable filter, the coefficient sets must be arranged by zigzag order. An example coefficient sets file in decimal format, 5x5 non-separable filter is given below: 0.0481 0.0936 0.1169 0.0936 0.0481 0.0936 0.1824 0.2278 0.1824 0.0936 0.1169 0.2278 0.2844 0.2278 0.1169 0.0936 0.1824 0.2278 0.1824 0.0936 0.0481 0.0936 0.1169 0.0936 0.0481 For separable filters, the horizontal vector is first, followed by the vertical vector. 0.2193 0.4271 0.5333 0.4271 0.2193 0.2193 0.4271 0.5333 0.4271 0.2193 The command line for executing coeffgen.tcl is >> tclsh coeffgen.tcl –lpc lpcFile –txt txtFile –map mapFile where: • lpcFile is the path to the parameter file, • txtFile is the path to an output text file containing the filter coefficients, and IPUG89_1.0, January 2011 11 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description • mapFile is the path to an output file containing the coefficient memory map. The lpcFile argument is required. The txtFile is in a format appropriate for use as the “Coefficients file” input in the 2D-FIR Filter IPexpress GUI for coefficient memory initialization. The IP generation scripts provide the memory mapping function. The mapFile contains row addresses and coefficient values after memory mapping is performed. The intended use is as a guide for in-system loading of coefficients via the coefficient update bus. Dynamic Zoom and Pan The 2D FIR Filter may be configured to allow the user to dynamically alter the decimation factors, as well as the coordinates of the active region of the input frame. The combination enables a dynamic zoom and pan capability. With dynamic decimation enabled at core generation time, two optional ports become available: decimx_in and decimy_in. The values on these ports determine the 2D FIR Filter’s decimation factors. The effective decimation factor will be 1 greater than the port value. The maximum decimation factors selected in the 2D FIR Filter’s IPexpress GUI determine the size of the ports. For decimating filters, the minimum decimation factors determine the number of multipliers that will be available in the hardware. For example, a 5x5 non-symmetric, non-separable kernel must perform 25 multiplies per output. However, if the decimation factors will always be at least 2, there will be at least 4 clock cycles available to calculate an output pixel value. The number of multipliers required will be ceil (25/4), or 7. For interpolating filters, the number of multipliers is a function of the interpolation factors and window size. The active region concept is illustrated in Figure 2-4. Figure 2-4. Active Region 0,0 upleftx, uplefty Active Region upleftx+actwidth, uplefty+actheight VWIDTH_IN, VHEIGHT_IN The upleftx and uplefty ports set the coordinates of the first pixel in the input frame that will have a corresponding pixel in the output frame. The actwidth and actheight ports determine the region of pixels in the input frame that will have corresponding pixels in the output frame. For example, if the scaling factors in X and Y are 3/2, in order to maintain a constant frame size from input to output, the active region must be 2/3 the width and height of the input frame. The interpolation/decimation factors and the active region dimensions define the zoom characteristics of the scaler. The upleft coordinates provide the pan capability. All three sets of inputs – upleft, active region, and decimation factors – are synchronized internally and delivered to the core logic at the appropriate time to avoid anomalies when moving from frame to frame. IPUG89_1.0, January 2011 12 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Functional Description Primary I/O Table 2-1. Primary I/O Port Size I/O Description clk 1 I System clock rstn 1 I System wide asynchronous active-low reset signal ce 1 I Active high clock enable (optional) sr 1 I Active high synchronous reset (optional) ready 1 O Core is ready for input dvalid_in 1 I Input valid frmsync_in 1 I Current pixel is at row 0, column 0 4 - 24 I Pixel data in 1 O Output valid Global Signals Video Input din Video Output dvalid_out frmsync_out dout 1 O Current output pixel is at row 0, column 0 4 - 24 O Pixel data out Interface Descriptions Video Input/Output The 2D FIR Filter uses a simple handshake to pass pixel data into the core. The core asserts its ready output when it is ready to receive data. When the driving module has data to give the core, it drives the core’s dvalid_in port to a ‘1’ synchronously with the rising edge of the clk signal, providing the input pixel data on port din. The frmsync_in input should be driven to a ‘1’ during the clock cycle when the first pixel of the first row in the incoming video frame is active. Correspondingly, dvalid_out is active when valid output pixel data is available on dout, and frmsync_out marks the first pixel, first row of the output video frame. Note: Output data for interpolating or decimating filter configurations can be quite bursty. Within a row, output pixels emerge in clusters whose size is determined by the interpolation and decimation factors. The spacing of the clusters may depend on the input data rate. During interpolated rows, the core de-asserts its ready signal, since it uses data already in the line buffers to calculate output pixel rows. Also, during interpolated rows, output data emerges at as high a rate as possible (for given interpolation values), not limited by the input data rate. When using the 2DFIR Filter IP core in a system with continuously streaming data, FIFOs may be required to remove the burstiness from the data flow. Coefficient Update The optional coefficient update port provides a write-only capability for modifying coefficient values. The port is synchronous with the rising edge of clk. To write a coefficient, set coeffwrite to ‘1’, coeffaddr to the concatenated row/column address of the coefficient to be written, and set coeffwdat to the value to be written. If the core was configured with double coefficient memories, all write operations affect only the standby memory, and the active coefficient values are not affected. To make the standby coefficient set active, set the coeffswap input to a ‘1’. The coeffswap_pending output will be a ‘1’ on the next clock cycle, and remain in that state until the active/standby swap occurs (sometime during the next frame). IPUG89_1.0, January 2011 13 2D FIR Filter IP Core User’s Guide Chapter 3: Parameter Settings The IPexpress tool is used to create IP and architectural modules in the Diamond or ispLEVER software. Refer to “IP Core Generation” on page 19 for a description of how to generate the IP. The 2D FIR IP core can be customized to suit a specific application by adjusting parameters prior to core generation. Since the values of some parameters affect the size of the resultant core, the maximum value for these parameters may be limited by the size of the target device. Table 3-1 provides the list of user configurable parameters for the 2D FIR IP core. Table 3-1. 2D FIR Filter IP Core Parameters. Parameter Range Data Input Width Default 4-24 8 Video Frame Width 100-2000 704 Video Frame Height 100-1200 480 Coefficients Width 4-24 8 Coefficients Type SIGNED or UNSIGNED UNSIGNED 1-31 3 Filtering Window Width Filtering Window Height 1-31 3 Edge Mode VALUE, COPY, MIRROR COPY Edge Value 0 - (1 Regenerate IP/Module. 2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. 4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension. 5. Click Next. The IP core’s dialog box opens showing the current option settings. 6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG89_1.0, January 2011 25 2D FIR Filter IP Core User’s Guide Chapter 7: Support Resources Lattice Technical Support There are a number of ways to receive technical support as listed below. Online Forums The first place to look is Lattice Forums (www.latticesemi.com/support/forums.cfm). Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers. Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m. Pacific Time. • For USA and Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • techsupport@latticesemi.com • techsupport-asia@latticesemi.com Local Support Contact your nearest Lattice sales office. Internet www.latticesemi.com References LatticeECP2/M • HB1003, LatticeECP2/M Family Handbook LatticeECP3 • HB1009, LatticeECP3 Family Handbook LatticeXP2 • DS1009, Lattice XP2 Datasheet Revision History Date Document Version January 2011 01.0 IPUG89_1.0, January 2011 IP Core Version Change Summary Initial release. 26 2D FIR Filter IP Core User’s Guide Appendix A: Resource Utilization This appendix gives resource utilization information for Lattice FPGAs using the 2D FIR Filter IP core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at  www.latticesemi.com. LatticeECP2 Devices Table A-1. Performance and Resource Utilization1 IP Core Configuration config1 config2 config3 Fmax Requirment(MHz) 125 170 179 Fmax Preference(MHz) 200+100 200+100 200+100 Fmax(MHz) 148 201 211 Start point 1 3 1 Core Utilization Reg. # 919 460 401 Total LUT4 # 2000 573 672 SLICES # 1368 422 431 IOB # 23 23 23 EBR # 2 2 2 MULT18X18 9 10 6 1. Performance and utilization data are generated targeting an LFE2-50E-6F484C device using Lattice Diamond 1.1 and Synplify Pro for Lattice D-2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticECP2 family. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeECP2/M devices is 2D-FIR-P2-U1. IPUG89_1.0, January 2011 27 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Resource Utilization LatticeECP2M Devices Table A-2. Performance and Resource Utilization1 IP Core Configuration config1 config2 config3 Fmax Requirment(MHz) 124 169 177 Fmax Preference(MHz) 200+100 200+100 200+100 Fmax(MHz) 147 199 209 Start point 2 1 1 Reg. # 919 460 401 Total LUT4 # 2000 573 672 SLICES # 1368 422 431 Core Utilization IOB # 23 23 23 EBR # 2 2 2 MULT18X18 9 10 6 1. Performance and utilization data are generated targeting an LFE2M50E-6F484C device using Lattice Diamond 1.1 and Synplify Pro for Lattice D-2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeECP2/M devices is 2D-FIR-PM-U1. LatticeECP3 Devices Table A-3. Performance and Resource Utilization1 IP Core Configuration config1 config2 config3 Fmax Requirment(MHz) 109 172 170 Fmax Preference(MHz) 200+100 200+100 200+100 Fmax(MHz) 129 203 201 Start point 2 1 2 924 460 404 Core Utilization Reg. # Total LUT4 # 2155 626 622 SLICES # 1412 429 407 IOB # 23 23 23 EBR # 2 2 2 MULT18X18 9 10 6 1. Performance and utilization data are generated targeting an LFE3-17EA-7FN484C device using Lattice Diamond 1.1 and Synplify Pro for Lattice D-2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeECP3 devices is 2D-FIR-E3-U1. IPUG89_1.0, January 2011 28 2D FIR Filter IP Core User’s Guide Lattice Semiconductor Resource Utilization LatticeXP2 Devices Table A-4. Performance and Resource Utilization1 IP Core Configuration config1 config2 config3 Fmax Requirment(MHz) 98 135 143 Fmax Preference(MHz) 200+100 200+100 200+100 Fmax(MHz) 116 159 169 Start point 3 2 2 Reg. # 919 460 401 Total LUT4 # 2000 573 672 SLICES # 1368 422 431 Core Utilization IOB # 23 23 23 EBR # 2 2 2 MULT18X18 9 10 6 1. Performance and utilization data are generated targeting an LFXP2-40E-6F484C device using Lattice Diamond 1.1 and Synplify Pro for Lattice D-2010.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeXP2 devices is 2D-FIR-X2-U1. IPUG89_1.0, January 2011 29 2D FIR Filter IP Core User’s Guide