8600V

ispLSI 8600V ® 3.3V In-System Programmable SuperBIG™ High Density PLD Features • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 32,000 PLD Gates/600 Macrocells — 192-264 I/O Pins Supporting 3.3V/2.5V I/O — 864 Registers — High-Speed Global and Big Fast Megablock (BFM) Interconnect — Wide 20-Macrocell Generic Logic Block (GLB) for High Performance — Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc. — PCB-Efficient Ball Grid Array (BGA) Package Options • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 8.5 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture, Symmetrical Generic Logic Blocks Connected by Hierarchical Big Fast Megablock and Global Routing Planes — Product Term Sharing Array Supports up to 28 Product Terms per Macrocell Output — Macrocells Support Concurrent Combinatorial and Registered Functions — Embedded Tristate Bus Can Be Used as an Internal Tristate Bus or as an Extension of an External Tristate Bus — Macrocell and I/O Registers Feature Multiple Control Options, Including Set, Reset and Clock Enable — I/O Pins Support Programmable Bus Hold, Pull-Up, Open-Drain and Slew Rate Options — Separate VCCIO Power Supply to Support 3.3V or 2.5V Input/Output Logic Levels — I/O Cell Register Programmable as Input Register for Fast Setup Time or Output Register for Fast Clock to Output Time 2 ® • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram 12 I/O 12 I/O 12 I/O 12 I/O 12 I/O 12 I/O 12 I/O Big Fast Megablock 0 12 I/O 12 I/O Big Fast Megablock 1 12 I/O 12 I/O Big Fast Megablock 2 Global Routing Plane 12 I/O 12 I/O Big Fast Megablock 3 12 I/O 12 I/O Big Fast Megablock 4 12 I/O Boundary Scan 12 I/O 12 I/O 12 I/O 12 I/O 12 I/O 12 I/O 8600v block ispLSI 8000V Family Description The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macrocells and a Global Routing Plane (GRP) structure interconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 120 registered macrocells arranged in six groups of 20, a group of 20 being referred to as a Generic Logic Block, or GLB. Within the Big Fast Megablock, a Big Fast Megablock Routing Pool (BRP) interconnects the six GLBs to each other and to 24 Big Fast Megablock I/O cells with optional I/O registers. The Global Routing Plane which interconnects the Big Fast Megablocks has additional global I/Os with optional I/O registers. The 192-I/O version contains 72 Big Fast Megablock I/O and 120 global I/O, while the 264-I/O Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com July 2000 8600v_03 1 Specifications ispLSI 8600V Functional Block Diagram Figure 1. ispLSI 8600V Functional Block Diagram (Perspective) Big Fast Megablock Routing Pool (BRP) Big Fast Megablock Routing Pool (BRP) Big Fast Megablock Routing Pool (BRP) Big Fast Megablock Routing Pool (BRP) Global Routing Plane (GRP) with Tristate Bus Lines 2 Specifications ispLSI 8600V ispLSI 8000V Family Description (Continued) version contains 120 Big Fast Megablock I/O and 144 global I/O. Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive any or all the Big Fast Megablocks in the device. This mechanism allows fast, efficient connections, both within the Big Fast Megablocks and between them. Each GLB contains 20 macrocells and a fully populated, programmable AND-array with 82 logic product terms. The GLB has 44 inputs from the Big Fast Megablock Routing Pool which are available in both true and complement form for every product term. Up to 20 of these inputs can be switched to provide local feedback into the GLB for logic functions that require it. The 80 general-purpose product terms can be grouped into 20 sets of four and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 28 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of four product terms or less. The 20 registered macrocells in the GLB are driven by the 20 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. Each macrocell has two outputs, one output can be fed back inside the GLB to the ANDarray, while the other output drives both the Big Fast Megablock Routing Pool and the Global Routing Plane. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. Macrocell registers can be clocked from one of several global, local or product term clocks available on the device. A global, local and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term signals. The polarity of all of these control signals is selectable on an individual macrocell basis. The macrocell register can be programmed to operate as a D-type register, a D-type flow-through latch or a T-type flip flop. The 20 outputs from the GLB can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. The Big Fast Megablock Routing Pool contains general purpose tracks which interconnect the six GLBs within the Big Fast Megablock and dedicated tracks for the signals from the Big Fast Megablock I/O cells. The Global Routing Plane contains general purpose tracks that interconnect the Big Fast Megablocks and also carry the signals from the I/Os connected to the Global Routing Plane. Control signals for the I/O cell registers are generated using an extra product term within each GLB, or using dedicated input pins. Each GLB has two extra product terms beyond the 80 available for the macrocell logic. The first additional product term is used as an optional shared product term clock for all the macrocells within the GLB. The second additional product term is then routed to an I/O Control Bus using a separate routing structure from the Big Fast Megablock Routing Pool and Global Routing Plane. Use of a separate control bus routing structure allows the I/O registers to have many control signals with no impact on the interconnection of the GLBs and Big Fast Megablocks. The I/O Control Bus is split into four quadrants, each servicing the I/O cell control requirements for one edge of the device. Signals in the control bus can be independently selected by any or all I/O cells to act as clock, clock enable, output enable, reset or preset. Each Big Fast Megablock has 24 I/O cells. The Global Routing Pool has 144 I/O cells. Each I/O cell can be configured as a combinatorial input, combinatorial output, registered input, registered output or bidirectional I/O. I/O cell registers can be clocked from one of several global, local or product term clocks which are selected from the I/O control bus. A global and product term clock enable is also provided, eliminating the need for the user to gate the clock to the I/O cell registers. Reset and preset for the I/O cell register is provided from both global and product term signals. The polarity of all of these control signals is selectable on an individual I/O cell basis. The I/O cell register can be programmed to operate as a Dtype register or a D-type latch. The input thresholds are fixed at levels which comply with both 3.3V and 2.5V interfaces. The output driver can source 4mA and sink 8mA (3.3V output supply). The output drivers have a separate VCCIO power supply which is independent of the main VCC supply for the device. This feature allows the output drivers to run from either 3.3V or 2.5V while the device logic is always 3 Specifications ispLSI 8600V ispLSI 8000V Family Description (Continued) powered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by another device. The ispLSI 8000V Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface using the JTAG protocol. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. Embedded Tristate Bus There is a 108-line embedded internal tristate bus as part of the Global Routing Plane (GRP), enabling multiple GLBs to drive the same tracks. This bus can be partitioned into various bus widths such as twelve 9-line buses, six 18-line buses or three 36-line buses. The GLBs can dynamically share a subset of the Global Routing Plane tracks. This feature eliminates the need to convert tristate buses to wide multiplexers on the programmable device. Up to 18 macrocells per GLB can participate in driving the embedded tristate bus. The remaining two macrocells per GLB are used to generate the internal tristate driver control signals on each data byte (with parity). The embedded tristate bus can also be configured as an extension of an external tristate bus using the bidirectional capability of the I/O cells connected to the Global Routing Plane. The Global Routing Plane I/Os 0-8 and 15-23 from each group (I/OGx as defined in the I/O Pin Location Table) can connect to the internal tristate bus as well as the unidirectional/nontristate global routing channels. I/Os 9-14 connect only to the global routing channel. The embedded tristate bus has internal bus hold and arbitration features in order to make the function more “user friendly”. The bus hold feature keeps the internal bus at the previously driven logic state when the bus is not driven to eliminate bus float. The bus arbitration is performed on a “first come, first served” priority. In other words, once a logic block drives the bus, other logic blocks cannot drive the bus until the first releases the bus. This arbitration feature prevents internal bus contention when there is an overlap between two bus enable signals. Typically, it takes about 3ns to resolve one bus signal coming off the bus to another bus signal driving the bus. The arbitration feature, combined with the predictability of the CPLD, makes the embedded tristate bus the most practical for real world bus implementation. ispLSI 8600V Description The ispLSI 8600V device has five Big Fast Megablocks for a total of 5 x 120 = 600 macrocells. Each Big Fast Megablock has a total of 24 I/O cells and the Global Routing Plane has a total of 144 I/O cells. This gives (5 x 24) + 144 = 264 I/Os for the full I/O version, while the partial I/O version contains 72 BFM I/O + 120 Global I/O = 192 I/Os. The total registers in the device is the sum of macrocells plus I/O cells, 600 + 264 = 864 registers. 4 Specifications ispLSI 8600V Figure 2. ispLSI 8000V GLB Overview I/O Big Fast Megablock Input Tracks AND Array Input Routing 0 General Purpose Big Fast Megablock Input Tracks Feedback Inputs 20 Product Term Sharing Array 43 PT 0 PT 1 PT 2 PT 3 Macrocell 0 From PTSA PTSA Bypass Single PT PT Clock PT Preset PT Reset Shared PT Clock Bus Input To Interconnect 0 From Tristate Bus Track PT 4 PT 5 PT 6 PT 7 Macrocell 1 From PTSA PTSA Bypass Single PT PT Clock PT Preset PT Reset Shared PT Clock Bus Input To Interconnect 1 From Tristate Bus Track PT 8 PT 9 PT 10 PT 11 Macrocell 2 From PTSA PTSA Bypass Single PT PT Clock PT Preset PT Reset Shared PT Clock Bus Input To Interconnect Fully Populated AND Array 2 From Tristate Bus Track PT 12 PT 13 PT 14 PT 15 Macrocell 3 From PTSA PTSA Bypass Single PT PT Clock PT Preset PT Reset Shared PT Clock Bus Input To interconnect 3 From Tristate Bus Track PT 76 PT 77 PT 78 PT 79 Macrocell 19 From PTSA PTSA Bypass Single PT PT Clock PT Preset PT Reset Shared PT Clock Bus Input To Interconnect 19 PT 80 From Tristate Bus Track PT 81 To Output Control MUX Note: Macrocells 9 and 10 do not support Tristate Bus Feedback. Function Selector (E2 Cell Controlled) 5 Specifications ispLSI 8600V Figure 3. ispLSI 8000V Macrocell Overview Bus Input From Tristate Bus Track* Feedback to AND Array PTSA PTSA Bypass PT Clock Clk En Global Clock Enable Global Clock 0 Global Clock 1 Global Clock 2 Single PT D Q To Big Fast Megablock or Global Interconnect To Specific Global Tristate Bus* R/L RP From Macrocell 9 or 10 PT Reset GRST PT Preset Reset pin GRST To All Macrocells and I/O Cells Preset/Reset Input has Global Polarity Control From PT80 *Not available for Macrocells 9 and 10. : Function Selector (E2 Cell Controlled) 6 Specifications ispLSI 8600V Figure 4. ispLSI 8000V I/O Cell TOE VCCIO VCCIO VCCIO GLOBAL OE0 GLOBAL OE1 GLOBAL OE2 GLOBAL OE3 From Output Control Bus Multiplexed Output From Big Fast Megablock or Global Track GLOBAL I/O CLOCK ENABLE From Output Control Bus D Q Big Fast Megablock I/O Pad or Global I/O Pad Slew Open Rate Drain CLKEN GLOBAL CLOCK0 GLOBAL CLOCK2 QUADRANT I/O CLOCK R/L To Specific Big Fast Megablock or Global Tracks To Specific Global Tristate Bus From Output Control Bus P R From Output Control Bus Global I/O Cell Only GRST From Output Control Bus : Function Selector (E2 Cell Controlled) 7 Specifications ispLSI 8600V Output Control Organization In addition to the data input and output to the I/O cells, each I/O cell can have up to six different I/O cell control signals. In addition to the internal OE control, the five control signals for each I/O cell consist of pin OE control, clock enable, clock input, asynchronous preset and asynchronous reset. All of the I/O control signals can be driven either from the dedicated external input pins or from the internal control bus. The output enable of each I/O cell can be driven by 21 different sources – 16 from the output control bus, four from the Global OE pins and one from the Test OE pin. The Global OE signals and Test OE signal are driven from the dedicated external control input pins. The 16-bit wide output control buses are organized in four different quadrants as shown in Figure 5. Since each GLB is capable of generating the output control signals, each of the output control bus signals can be driven from a unique GLB. The 30 GLBs can generate a total of 30 unique I/O control signals. Referring to Figure 2, the GLB generates its output control signal from control product term (PT81). Figure 5 also illustrates how the quadrant clocks are routed to the appropriate quadrant I/O cells. Figure 5. Output Control Bus and Quadrant Organization Quadrant 0, 16-Bit Wide Output Control Bus (I/O B0-B4 , QIOCLK0) Quadrant 1, 16-Bit Wide Output Control Bus (I/O G0-G5 , QIOCLK1) GLB Generated Output Control (see Figure 2) From PT81 Quadrant 2, 16-Bit Wide Output Control Bus (I/O B0-B4 , QIOCLK2) OE Bus/8600V.eps 8 Quadrant 3, 16-Bit Wide Output Control Bus (I/O G0-G5 , QIOCLK3) Specifications ispLSI 8600V Figure 6. Boundary Scan Register Circuit for I/O Pins HIGHZ EXTEST PROG_MODE SCANIN (from previous cell) BSCAN Registers D Q BSCAN Latches D Q TOE Normal Function OE 0 1 EXTEST PROG_MODE Normal Function 0 1 I/O Pin D Q D Q D Q SCANOUT (to next cell) Shift DR Clock DR Update DR Reset* *Internal power-up reset signal. Not connected to external reset pin. Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell Shift DR Clock DR D Q SCANOUT (to next cell) 9 Specifications ispLSI 8600V Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp Tbtvo TDO Valid Data Tbtco Valid Data Tbtoz Tbtcpsu Data to be captured Tbtcph Data Captured Tbtuov Data to be driven out Tbtuco Valid Data Tbtuoz Valid Data SYMBOL PARAMETER TCK Clock Pulse Width TCK Pulse Width High TCK Pulse Width Low TDI, TMS Setup Time to TCK TDI, TMS Hold Time from TCK TCK, TDI, TMS Rise and Fall Time TAP Controller, TCK to TDO Valid TAP Controller, TCK to TDO High-Impedance TAP Controller, TCK to TDO High-Impedance to Valid Output BSCAN Test Capture Register Setup Time BSCAN Test Capture Register Hold Time BSCAN Test Update Register Clock to Valid Output BSCAN Test Update Register Clock to High-Impedance BSCAN Test Update Register High-Impedance to Valid Output MIN 100 50 50 25 25 50 — — — 25 25 — — — MAX — — — — — — 25 25 25 — — 65 65 65 UNITS ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns tbtcp tbtch tbtcl tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov Table 2-0010/8600V 10 Specifications ispLSI 8600V Absolute Maximum Ratings 1,2 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL PARAMETER Supply Voltage I/O Supply Voltage Commercial TA = 0°C to 70°C MIN. 3.0 2.3 MAX. 3.6 3.6 UNITS V V Table 2-0005/8600V VCC VCCIO Capacitance (TA=25°C,f=1.0 MHz) SYMBOL PARAMETER I/O Capacitance Clock Capacitance Global Input Capacitance TYPICAL 10 10 10 UNITS pf pf pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VCK = 2.0V VCC = 3.3V, VG = 2.0V Table 2-0006/8600V C1 C2 C3 Erase/Reprogram Specification PARAMETER Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM – UNITS Cycles Table 2-0008/8600V 11 Specifications ispLSI 8600V Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to VCCIOmin ≤ 1.5 ns 10% to 90% 1.5V 1.5V See Figure 9 Table 2-0003/8600V Figure 9. Test Load VCCIO R1 Device Output R2 CL* Test Point Output Load Conditions (See Figure 9) 3.3V TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V Slow Slew R1 ∞ 316Ω ∞ 316Ω ∞ R2 348Ω ∞ 348Ω ∞ ∞ 2.5V R1 ∞ 511Ω ∞ 511Ω ∞ R2 CL 316Ω 348Ω 511Ω 475Ω 35pF 475Ω 35pF ∞ 475Ω ∞ ∞ 35pF 5pF 5pF 35pF *CL includes Test Fixture and Probe Capacitance. 0213A/8600V C D Table 2-0004A/8600V DC Electrical Characteristics for 3.3V Range Over Recommended Operating Conditions SYMBOL PARAMETER I/O Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 8 mA IOH = -4 mA CONDITION TA = 0°C to + 70°C MIN. 3.0 -0.3 2.0 – 2.4 MAX. UNITS 3.6 0.8 5.25 0.4 – V V V V V VCCIO VIL VIH VOL VOH Table 2-0007/8600V DC Electrical Characteristics for 2.5V Range Over Recommended Operating Conditions SYMBOL PARAMETER I/O Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCCIO=min, VIN=VIH or VIL, IOL= 100µA VCCIO=min, VIN=VIH or VIL, IOL= 2mA VCCIO=min, VIN=VIH or VIL, IOH= -100µA VCCIO=min, VIN=VIH or VIL, IOH= -2mA CONDITION TA = 0°C to + 70°C MIN. 2.3 -0.3 1.7 – – 2.1 1.7 MAX. 2.7 0.7 5.25 0.2 0.7 – – UNITS V V V V V V V VCCIO VIL VIH VOL VOH Table 2-0007B/8600V 12 Specifications ispLSI 8600V DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Input or I/O Low Leakage Current Input or I/O High Leakage Current 4 CONDITION 0V ≤ VIN ≤ VIL (Max.) (VCCIO-0.2)V ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL VIN = VIL(max) VIN = VIH(min) 0V ≤ VIN ≤ VCCIO 0V ≤ VIN ≤ VCCIO VIL = 0.5V, VIH = 3.0V High Speed Mode fTOGGLE = 1 MHz Low Power Mode MIN. – – – – 40 -40 – – VIL – – TYP. – – – – – – – – – 330 160 2 MAX. UNITS -10 10 50 -250 – – 550 -550 VIH – – µA µA µA µA µA µA µA µA V mA IIL IIH IPU IBHL IBHH IBHLO IBHLH IBHT ICC1,3,5 1. 2. 3. 4. 5. I/O Active Pullup Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Operating Power Supply Current Measured at a frequency of 1MHz using 30 20-bit counters. Typical values are at VCC = 3.3V and TA = 25°C. Maximum ICC varies widely with specific device configuration and operating frequency. Pullup is capable of pulling minimum voltage of VOH under no-load conditions. Unused inputs held at GND. Table 2-0007C/8600V 13 Specifications ispLSI 8600V External Switching Characteristics1 Over Recommended Operating Conditions PARA- TEST 2 4# METER COND. DESCRIPTION -125 — — 3 -90 — — 90.0 8.0 — 0.0 — 6.0 0.0 — 7.0 0.0 — 6.5 0.0 4.5 0.0 — — — 6.5 6.0 6.0 10.0 16.0 — — — 6.0 — — 7.5 — — 10.0 — — — — 10.0 15.0 10.0 — — — -60 — — 60.0 12.0 0.0 — 9.0 0.0 — 10.0 0.0 — 9.5 0.0 6.5 0.0 — — — 9.5 9.0 9.0 15.0 24.0 — — — 9.0 — — 11.0 — — 15.0 — — — — 15.0 22.0 15.0 — — — MIN. MAX. MIN. MAX. MIN. MAX. 8.5 13.5 — UNITS ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax tsuq thq tcoq tsug thg tcog tsu1 th1 tco1 tsuceq thceq tsuceg thceg tgoe trglb trio trw twh twl 1. 2. 3. 4. A A — — — A — — A — — A — — — — B/C — — — — — 1 Prop Delay, BFM Input to Same BFM Output, 4 PT Bypass 2 Prop Delay, Global Input to Global Output 3 Clk Frequency, Local Feedback, Same GLB 4 I/O Cell Reg, Data Setup Time, Quadrant I/O Clock 5 I/O Cell Reg, Data Hold Time, Quadrant I/O Clock 6 I/O Cell Reg, Quadrant Clock to Output Delay 7 I/O Cell Reg, Data Setup Time, Global Clock 8 I/O Cell Reg, Data Hold Time, Global Clock 9 I/O Cell Reg, Global Clock to Output Delay 10 GLB Reg Setup, BFM Input to Same BFM GLB, 4 PT Bypass 11 GLB Reg Hold Time, BFM Input to Same BFM GLB 12 GLB Reg, Global Clock to Same BFM Output Delay 13 I/O Cell Reg, CLKEN Setup Time, Quadrant I/O Clock 14 I/O Cell Reg, CLKEN Hold Time, Quadrant I/O Clock 15 GLB Reg, CLKEN Setup Time, Global Clock 16 GLB Reg, CLKEN Hold Time, Global Clock 17 Global Output Enable/Disable Delay 18 Global Reset/Preset Time, GLB Reg 19 Global Reset/Preset Time, I/O Cell Reg 20 Global Reset/Preset Pulse Duration 21 Global or Quadrant Clock Pulse, High Duration 22 Global or Quadrant Clock Pulse, Low Duration 125.0 5.0 0.0 — 3.5 0.0 — 4.5 0.0 — 5.5 0.0 3.5 0.0 — — — 5.0 4.0 4.0 4.0 — — 6.0 — — 8.0 — — — — 7.0 14.0 8.5 — — — Unless noted otherwise, all parameters use PTSA and CLK0. Refer to Timing Model in this data sheet for further details. Standard 20-bit counter with local feedback. Refer to Switching Test Conditions section. Table 2-0030/8600V 14 Specifications ispLSI 8600V Internal Timing Parameters Over Recommended Operating Conditions PARAMETER -125 #2 DESCRIPTION MIN – – – – – – 0.5 2.5 – 0.9 4.6 – – – – – – – – – – – – – – 2.7 1.0 – 1.0 2.3 – 1.3 – 1.7 1.7 – – MAX 0.3 6.4 0.0 0.4 2.0 0.5 – – 1.5 – – 1.6 1.6 1.4 0.0 6.2 2.6 6.5 1.9 0.5 1.4 2.4 0.0 4.6 0.2 – – 2.0 – – 0.1 1.3 1.7 1.9 1.9 1.5 7.2 MIN – – – – – – 2.4 3.2 – 1.0 4.6 – – – – – – – – – – – – – – 4.5 1.2 – 1.3 2.6 – 1.6 – 2.0 2.0 – – -90 MAX 0.4 7.6 0.0 0.5 2.4 1.2 – – 1.7 – – 1.9 1.9 1.7 0.0 7.3 2.9 7.7 2.2 0.6 1.7 2.7 0.0 5.5 0.8 – – 1.5 – – 0.1 1.6 2.0 2.3 2.3 1.7 8.4 MIN – – – – – – 3.9 4.7 – 1.2 6.9 – – – – – – – – – – – – – – 6.9 1.1 – 1.7 3.9 – 2.5 – 3.1 3.1 – – -60 MAX 0.6 11.2 0.0 0.8 3.6 1.6 – – 2.5 – – 2.9 2.9 2.6 0.0 10.9 4.2 11.5 3.4 0.9 2.2 4.1 0.0 8.2 0.9 – – 1.6 – – 0.6 2.5 3.1 3.5 3.5 2.6 12.7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns I/O Cell Delay tidcom tidreg tobp tibp tiolat tioco tiosu tioh tiorst tiosuce tiohce todreg todcom todz tslf tsls tandhs tandlp t1pt t4ptcom t4ptreg tptsa tmbp tmlat tmco tmsu tmh tmrst tmsuce tmhce tfloc tpck tpcken tsck tscken tprst trdir 23 Input Pad and Input Buffer, Combinatorial Input 24 Input Pad and Input Buffer, Registered Input 25 Output Register/Latch Bypass to Output Buffer 26 Input Register/Latch Bypass to BFM Routing or GRP 27 I/O Cell Latch, Transparent Mode 28 I/O Cell Register/Latch, Clk/Gate to Output 29 I/O Cell Register/Latch, Setup Time 30 I/O Cell Register/Latch, Hold Time 31 I/O Cell Register/Latch, Reset or Set Time 32 I/O Cell Register/Latch, Setup Time for Clk Enable 33 I/O cell Register/Latch, Hold Time for Clk Enable 34 I/O Cell Output Buffer Delay, Registered Output 35 I/O Cell Output Buffer Delay, Combinatorial Output 36 Output Driver Disable Time 37 Slew Rate Adder, Fast Slew Rate 38 Slew Rate Adder, Slow Slew Rate 39 AND Array, High Speed Mode 40 AND Array, Low Power Mode 41 Single Product Term Bypass 42 Four Product Term Bypass, Combinatorial Macrocell 43 Four Product Term Bypass, Registered Macrocell 44 Product Term Sharing Array 45 Macrocell Register/Latch Bypass 46 Macrocell Latch, Transparent Mode 47 Macrocell Register/Latch, Clk/Gate to Output 48 Macrocell Register/Latch, Setup Time 49 Macrocell Register/Latch, Hold Time 50 Macrocell Register/Latch, Reset or Set Time 51 Macrocell Register/Latch, Setup Time for Clk Enable 52 Macrocell Register/Latch, Hold Time for Clk Enable 54 Local Feedback to AND Array 55 Single Product Term, Clk 56 Single Product Term, Clk Enable 57 Shared Product Term, Clk 58 Shared Product Term, Clk Enable 59 Single Product Term, Reset or Set Delay 60 Macrocell Register, Direct Input from GRP GLB / Macrocell Delay 15 Specifications ispLSI 8600V Internal Timing Parameters Over Recommended Operating Conditions PARAMETER -125 #2 DESCRIPTION MIN 0.4 – – – – – – – – – – – – – – – – 3.9 6.4 3.4 6.5 1.9 – – – – MAX 1.0 1.6 4.1 0.6 2.0 3.0 2.5 1.3 1.5 2.3 0.8 1.6 4.1 4.6 5.6 4.3 3.3 4.1 6.4 3.9 6.5 1.9 5.6 8.5 7.6 5.4 MIN 0.6 – – – – – – – – – – – – – – – – 4.3 7.5 4.0 7.5 2.0 – – – – -90 MAX 1.3 1.9 4.9 0.7 3.0 4.3 3.3 1.5 1.7 2.6 0.8 1.7 4.7 5.3 6.5 5.0 3.8 4.9 7.5 4.4 7.5 2.9 8.3 10.1 7.8 6.4 MIN 0.8 – – – – – – – – – – – – – – – – 6.6 11.4 6.1 11.4 3.1 – – – – -60 MAX 1.9 2.8 7.3 1.1 4.5 6.5 4.9 2.3 2.6 4.0 1.2 2.6 7.2 8.1 9.9 7.6 5.8 7.5 11.4 6.5 11.4 4.5 12.4 15.2 11.8 9.6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns BFM / Global Routing Pool Delay tbfmi tgrpi tgrpiz tbfmm tgrpm tgrpmz tbfmg tgrpb tbcom tbreg tgcom tgreg tpiock tpiocken tpoe tpiorst tpioz tgck tgcken tgiock tgiocken tqck tgoe ttoe tgmrst tgiorst 61 BFM Routing Delay, Signal from I/O Cell 62 GRP Delay, Signal from I/O Cell 63 Internal Tristate Bus Enable/Disable, I/O Cell Buffer 64 BFM Routing Delay, Signal from Macrocell 65 GRP Delay, Signal from Macrocell 66 Internal Tristate Bus Enable/Disable, Macrocell Buffer 67 BFM Routing Delay, Signal from GRP 68 GRP Delay, Signal from BFM Routing 69 BFM Routing to I/O Cell, Combinatorial Path 70 BFM Routing to I/O Cell, Registered Path 71 GRP to I/O Cell, Combinatorial Path 72 GRP to I/O Cell, Registered Path 73 Product Term as I/O Cell Register Clock 74 Product Term as I/O Cell Register Clock Enable 75 Product Term as Output Buffer Enable/Disable 76 Product Term as I/O Cell Register Reset or Set Delay 77 Internal Tristate Bus Control Signal for I/O Cell Buffer 78 Global Macrocell Register Clk 79 Global Macrocell Register Clk Enable 80 Global I/O Register Clk 81 Global I/O Register Clk Enable 82 Quadrant I/O Register Clk 83 Global Output Enable 84 Test Output Enable 85 Global GLB Register Reset 86 Global I/O Cell Register Reset I/O Control Bus Delay Global Control Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 16 Specifications ispLSI 8600V ispLSI 8600V Timing Model Input Buffer and I/O Cell Register I/O register delays I/O pad Input buffer delays #23, tidcom #24, tidreg #25, tobp #26, tibp #27, tiolat #28, tioco #29, tiosu #30, tioh #31, tiorst #32, tiosuce #33, tiohce Output path Input path #69, tbcom #70, tbreg #71, tgcom #72, tgreg Output routing Output buffer delays Output slew rate adders #34, todreg #35, todcom #36, todz #37, tslf #38, tsls I/O pad BFM Routing Pool GLB/ Macrocell #61, tbfmi #67, tbfmg #64, tbfmm z Local feedback #54, tfloc PTSA Macrocell Register AND array #39, tandhs #40, tandlp #41, t1pt #42, t4ptcom #43, t4ptreg #44, tptsa PT Mcell controls #55, tpck #56, tpcken #57, tsck #58, tscken #59, tprst PT I/O control bus #45, tmbp #46, tmlat #47, tmco #48, tmsu #49, tmh #50, tmrst #51, tmsuce #52, tmbce Bus direct Global Routing Plane #62, tgrpi #63, tgrpiz #65, tgrpm #66, tgrpmz #68, tgrpb #60, trdir Global control delay Input pad #78, tgck #79, tgcken #80, tgiock #81, tgiocken #82, tqck #83, tgoe #84, ttoe #85, tgmrst #86, tgiorst #73, tpiock #74, tpiocken #75, tpoe #76, tpiorst #77, tpioz 8840V_Model.eps 17 Specifications ispLSI 8600V Example Timing Calculations tpd1 = (BFM Input Path Delay) + (GLB Delay) + (Output Path Delay) = (tidcom + tibp + tbfmi max) + (tandhs + t4ptcom + tmbp) + (tbfmm + tbcom + tobp + todcom + tslf) = (#23 + #26 + #61) + (#39 + #42 + #45) + (#64 + #69 + #25 + #35 + #37) = (0.3 + 0.4 + 1.0) + (2.6 + 0.5 + 0.0) + (0.6 + 1.5 + 0.0 + 1.6 + 0.0) = 8.5 ns = (BFM Delay) + (GLB Delay) = (tbfmm) + (tandhs + t4ptcom + tmbp) = (#64) + (#39 + #42 + #45) = (0.6) + (2.6 + 0.5 + 0.0) = 3.7 ns tpd (within BFM) tpd (between BFMs) = (GRP Delay) + (BFM Delay) + (GLB Delay) = (tgrpm) + (tbfmg) + (tandhs + t4ptcom + tmbp) = (#65) + (#67) + (#39 + #42 + #45) = (2.0) + (2.5) + (2.6 + 0.5 + 0.0) = 7.6 ns BFM I/O to internal tri-state Enable/Disable = (BFM Input Path Delay) + (GLB Delay, 1PT) + (Tri-state Control Delay) = (tidcom + tibp + tbfmi max) + (tandhs + t1pt + tmbp) + (tgrpmz) = (#23 + #26 + #61) + (#39 + #41 + #45) + (#66) = (0.3 + 0.4 + 1.0) + (2.6 + 1.9 + 0.0) + (3.0) = 9.2 ns tsu1 = (BFM Input Path Delay) + (GLB Setup Time) - (Min. Global Clock Delay) = (tidcom + tibp + tbfmi max) + (tandhs + t4ptreg + tmsu) – (tgck min) = (#23 + #26 + #61) + (#39 + #43 + #48) – (#78) = (0.3 + 0.4 + 1.0) + (2.6 + 1.4 + 2.7) – (3.9) = 4.5 ns 1/Fmax = (Global Clk to MC Output) + (Local Feedback) + (GLB Setup Time) = (tmco) + (tfloc) + (tandhs + tptsa + tmsu) = (#47) + (#54) + (#39 + #44 + #48) = (0.2) + (0.1) + (2.6 + 2.4 + 2.7) = 8.0 ns Fmax = 125 MHz Note: Calculations are based upon timing specifications for the ispLSI 8600V-125L 18 Specifications ispLSI 8600V Power Consumption Power consumption in the ispLSI 8600V device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/power tradeoff setting. Each group of four product terms has a single speed/power tradeoff control fuse that acts on the complete group of four. The fast “high-speed” setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower “lowpower ” s etting will significantly reduce the power dissipation for these product terms. Figure 10 shows the relationship between power and operating speed. Figure 10. Typical Device Power Consumption vs fmax 600 500 ICC (mA) 400 300 200 100 0 0 10 20 30 40 ispLSI 8600V Turbo Non-Turbo 50 60 70 80 90 100 110 120 130 fmax (MHz) Notes: Configuration of 30 20-bit counters Typical current at 3.3V, 25¡ C ICC can be estimated for the ispLSI 8600V using the following equation: ICC = 25.0 + (# of Turbo PTs * 0.25) + (# of Non-Turbo PTs * 0.11) + (# of Macrocells Used * fmax * AF * 0.04) # of Turbo PTs = Number of Turbo Product Terms Used in Design # of Non-Turbo PTs = Number of Non-Turbo Product Terms Used in Design fmax = Maximum Operating Frequency AF (Activity Factor) = Average Macrocell Toggle Frequency Fmax Note: An Activity Factor of 1.0 means all macrocell registers toggle at fmax. An Activity Factor of 0.5 means the average macrocell register toggles at half of fmax. The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/8600V 19 Specifications ispLSI 8600V Signal Descriptions Signal Name CLK0, CLK1, CLK2 CLKEN Description Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock inputs of all GLB registers in the device. Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate the clock to the register. Ground (GND) Global Output Enable inputs. Dedicated, reset/preset pin connected to ALL registers in the device, GLB registers and I/O registers. Each register can independently choose to be reset or preset when this signal goes active. The active polarity is user selectable. Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the clock to the I/O register. Input/Output – These are the general purpose I/O used by the logic array. Embedded Port Enable Pin – When this pin is high, the port is enabled. When this pin is low, the state machine is held at reset asynchronously and TCK, TMS and TDI are ignored. Input – This signal is the Test Mode Select input signal. Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers on the same side of the device only, they are not connected to all of the I/O registers. Use of these quadrant I/O clocks gives the fastest tco from the device. Input – This signal is the Test Clock input signal. Input – This signal is the Test Data input signal. Output – This signal is the Test Data Out Output Signal. Test Output Enable. Tristates all I/O pins when a logic low is driven. Vcc Power supply for the output drivers. The internal logic of the device is connected to VCC which is always 3.3V. The output drivers are connected to VCCIO which can be equal to VCC or 2.5V. This allows the output drivers to be powered from 2.5V, for example, to interface directly with another 2.5V device. No connect. GND GOE0, GOE1, GOE2, GOE3 SET/RESET IOCLKEN I/O EPEN TMS QIOCLK0, QIOCLK1, QIOCLK2, QIOCLK3 TCK TDI TDO TOE VCC VCCIO NC1 1. NC pins are not to be connected to any active signals, VCC or GND. 20 Specifications ispLSI 8600V Signal Locations Signal Name 272-Ball BGA QIOCLK0, QIOCKL1, Y8, M20, C8, N2 QIOCLK2, QIOCLK3 CLK0, CLK1, CLK2 CLKEN IOCLKEN EPEN TCK TDI TDO TMS GOE0, GOE1, GOE2, GOE3 TOE SET/RESET VCC Y9, P18, D8 V9 B9 C17 A4 U5 C4 W4 Y10, M19, C9, N1 L3 P3 D9, D10, D11, D12, J4, J17, K4, K17, L4, L17, M4, M17, U9, U10, U11, U12 492-Ball BGA AE14, P22, A15, N3 AC15, R24, B15 AB17 E16 B26 A2 AF1 B3 AC4 AF15, P23, D16, N5 L5 P2 E9, E12, E15, E18, F5, F10, F17, F22, G5, G22, K5, K22, L22, M5, N22, P5, R22, T5, U5, U22, Y5, Y22, AA5, AA10, AA17, AA22, AB9, AB12, AB15, AB18 E8, E13, E19, F7, F20, J6, J21, K3, L24, N1, P24, T3, U25, V6, Y23, AA7, AA20, AB8, AB14, AB19 E5, E11, E14, E22, F6, F21, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, AA6, AA21, AB5, AB13, AB16, AB22 A1, A6, A7, A8, A16, A20, A21, A22, , B1, B2, B7, B8, B9, B20, B21, C1, C2, C3, C7, C8, C9, C19, C20, C21, C24, C25, C26, D1, D2, D3, D4, D7, D8, D9, D19, D20, D21, D24,D25, D26, E6, E17, E20, E21, E23, E24, E25, E26, F8, F9, F18, F19, G6, G21, Y6, Y21, AA8, AA9, AA18, AA19, AB1, AB2, AB3, AB4, AB6, AB10, AB20, AB21, AB23, AC1, AC2, AC3, AC6, AC7, AC8, AC18, AC19, AC20, AC23, AC24, AC25, AC26, AD1, AD2, AD3, AD6, AD7, AD8, AD15, AD19, AD20, AD25, AD26, AE1, AE6, AE7, AE8, AE19, AE20, AE21, AE25, AE26, AF6, AF7, AF8, AF19, AF20, AF21, AF25, AF26 VCCIO A7, A8, A20, B16, C5, C12, E4, G20, H4, M1, N17, U2, U20, V2, V6, W7, W8, W16, W19, Y13 D4, D16, D17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, U4, U17 GND NC1 A9, V17, W9 1. NC pins are not to be connected to any active signals, VCC or GND. 21 Specifications ispLSI 8600V I/O Pin Locations (272-Ball BGA Package) Signal BGA Signal BGA Signal BGA Signal BGA Signal BGA I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 V4 Y3 Y2 W3 Y1 W2 W1 V3 V1 U3 R4 T4 U19 R17 V20 V19 U18 V18 T17 W20 Y20 Y19 W18 Y18 U1 T3 T2 T1 R3 R2 R1 P4 P2 N4 N3 P1 N18 N19 N20 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 P19 P17 P20 R20 R19 R18 T20 T19 T18 H2 H1 J3 J2 J1 K3 K2 K1 L2 L1 M2 M3 M18 L20 L19 L18 K20 K19 K18 J20 H20 J19 H19 J18 G2 G1 H3 G3 G4 F3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 F1 F2 F4 E1 E2 E3 D20 F17 E19 G17 G18 F18 E20 F19 H17 F20 H18 G19 A3 B2 B3 A2 A1 B1 D3 D2 C3 C2 D1 C1 D19 E18 C20 B20 A19 C19 D18 B19 C18 I/O G5 I/O G5 I/O G5 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 E17 B18 A18 Y4 V5 W5 Y5 U6 U7 W6 V7 Y6 Y7 U8 V8 B8 C7 D7 B7 B6 C6 A6 D6 B5 A5 D5 B4 V10 W10 Y11 W11 V11 Y12 W12 V12 W13 U13 V13 Y14 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 B14 D13 B13 A13 A12 B12 B11 A11 C11 B10 A10 C10 W14 V14 U14 Y15 W15 V15 U15 Y16 V16 U16 W17 Y17 B17 A17 C16 D15 C15 A16 B15 D14 C14 A15 A14 C13 22 Specifications ispLSI 8600V I/O Pin Locations (492-Ball BGA Package) Signal BGA Signal BGA Signal BGA Signal BGA Signal BGA I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 AA4 AA3 AA2 AA1 Y4 Y3 Y2 Y1 W4 W3 W2 U6 U21 Y26 Y25 Y24 V21 AA26 AA25 AA24 AA23 AB26 AB25 AB24 T2 W5 U1 U2 U3 U4 V1 V5 V2 V3 V4 W1 W23 W24 W25 W26 V22 V23 V24 V25 V26 W22 U23 U24 T4 T1 W6 R2 R1 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 R3 R4 R5 P1 P3 P4 N4 P26 P25 R23 T22 R26 R25 T26 T23 W21 T24 T25 U26 K2 K1 L2 H6 L3 L4 L1 M2 M1 M3 M4 N2 N23 N24 N26 N25 M22 M23 M24 M26 H21 M25 L26 L23 K4 H5 J1 J2 J3 J4 H1 J5 H2 H3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 H4 K6 H26 J23 J24 J25 J22 J26 K23 K24 K25 H22 K26 L25 E4 E3 E2 E1 F4 F3 F2 F1 G4 G3 G2 G1 K21 H25 H24 H23 G26 G25 G24 G23 F26 F25 F24 F23 AE2 AF2 AE3 AF3 AD4 AE4 AF4 AC5 AD5 AE5 AB7 AF5 B6 E7 C6 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 I/O B2 D6 A5 B5 C5 D5 A4 B4 C4 A3 AC9 AD9 AE9 AF9 AC10 AD10 AE10 AF10 AE11 AD11 AB11 AC11 A12 E10 B12 A11 D11 C11 B11 A10 B10 C10 D10 A9 AF11 AE12 AF12 AD12 AC12 AE13 AF13 AD13 AC13 AC14 AD14 AF14 C15 D15 B14 A14 C14 D14 D13 C13 I/O B2 I/O B2 I/O B2 I/O B2 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 A13 B13 D12 C12 AE15 AF16 AC16 AD16 AE16 AF17 AE17 AD17 AC17 AF18 AE18 AD18 B19 A19 D18 C18 B18 A18 D17 C17 B17 A17 B16 C16 AD21 AC21 AF22 AE22 AD22 AC22 AF23 AE23 AD23 AF24 AE24 AD24 A26 D23 B25 A25 B24 A24 C23 B23 A23 D22 C22 B22 23 Specifications ispLSI 8600V Signal Configuration ispLSI 8600V 272-Ball BGA Signal Diagram 20 A B C D E F G H J K L M N P R T U V W Y VCCIO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 TCK 3 2 1 A B C D E F G H J K L M N P R T U V W Y I/O G5 I/O G5 I/O B4 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B3 NC1 VCCIO VCCIO IOCLKEN I/O B0 I/O B0 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B3 I/O B3 VCCIO I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O G5 I/O G5 I/O G5 QIOCLK 2 I/O G5 I/O G5 I/O G5 I/O B4 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 GOE EPEN VCCIO 2 I/O G4 I/O G5 I/O G5 GND I/O G4 I/O G4 I/O G5 I/O G5 I/O G4 I/O G4 I/O G4 I/O G4 VCCIO I/O B0 I/O B0 I/O G5 I/O G5 I/O G5 VCCIO TDO I/O G5 I/O G5 I/O G5 I/O B0 I/O B0 I/O B0 GND VCCIO GND I/O B4 I/O B4 I/O B3 VCC VCC VCC VCC CLK 2 I/O G4 I/O G4 I/O G4 ispLSI 8600V Bottom View GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 VCCIO I/O G4 I/O G4 I/O G4 I/O G3 I/O G3 I/O G4 I/O G4 I/O G3 I/O G3 I/O G3 VCC I/O G3 I/O G3 I/O G3 VCC I/O G3 I/O G3 I/O G3 VCC QIOCLK 1 I/O G4 I/O G3 I/O G3 VCC I/O G3 I/O G3 I/O G3 VCC I/O G3 I/O G3 I/O G3 VCC TOE I/O G3 I/O G3 GOE I/O G3 VCC 1 VCC I/O G3 I/O G3 VCCIO I/O G2 I/O G2 QIOCLK 3 I/O G2 I/O G2 I/O G2 VCCIO I/O G2 I/O G2 CLK 1 I/O G2 I/O G2 I/O G2 I/O G2 I/O G0 I/O G2 I/O G2 I/O G2 I/O G0 VCCIO GOE 3 I/O G2 SET/ I/O G2 I/O G2 RESET I/O G0 I/O G2 I/O G2 I/O G2 I/O G0 I/O G2 I/O G2 I/O G2 VCC VCC VCC I/O B0 I/O B0 I/O B0 TDI GND I/O G0 I/O G2 VCCIO I/O G0 I/O G0 I/O B4 I/O B4 I/O B4 I/O B3 GND VCC I/O G0 I/O G0 I/O G0 NC1 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B3 I/O B0 I/O B0 VCCIO I/O B0 I/O G0 I/O G0 VCCIO I/O G0 CLKEN NC1 VCCIO VCCIO I/O B0 I/O B0 QIOCLK 0 I/O G0 VCCIO I/O G0 I/O B4 VCCIO I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B3 TMS I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O G0 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 GOE CLK 0 VCCIO 0 I/O B0 I/O B0 I/O B0 I/O B0 I/O G0 I/O G0 I/O G0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package. 24 Specifications ispLSI 8600V Signal Configuration ispLSI 8600V 492-Ball BGA Signal Diagram 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF I/O B4 I/O B4 I/O B4 I/O B4 NC 1 9 8 NC1 NC1 NC1 NC1 7 NC1 NC1 NC1 NC1 6 NC1 5 4 3 2 1 NC1 NC1 NC1 NC1 NC 1 NC 1 I/O B3 I/O B3 I/O B3 NC 1 QIOCLK 2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 I/O B1 NC1 NC1 NC1 I/O B0 I/O B0 I/O B0 TCK NC1 NC1 NC1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF I/O B4 I/O B4 I/O B4 I/O B4 EPEN NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 I/O B4 I/O B4 I/O B4 I/O B4 NC1 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 I/O B3 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 CLK2 NC1 NC1 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 GOE 2 NC1 VCC IOCLKEN I/O B0 I/O B0 I/O B0 TDO I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 NC1 GND VCC NC1 NC1 NC1 NC1 VCCIO VCC NC1 VCC GND VCCIO VCC GND I/O B1 I/O B0 VCC VCCIO VCC NC1 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 I/O G5 VCC I/O G5 I/O G5 I/O G5 I/O G5 VCC GND VCCIO NC1 NC1 NC1 VCCIO GND 1 NC I/O G5 I/O G5 I/O G5 I/O G5 VCC I/O G4 I/O G5 I/O G5 I/O G5 I/O G4 I/O G3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 VCCIO I/O G5 I/O G4 I/O G4 I/O G4 I/O G4 VCC I/O G3 I/O G4 I/O G3 VCCIO VCC I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 I/O G3 VCC I/O G2 I/O G2 VCCIO GOE 1 QIOCLK 1 I/O G2 I/O G2 I/O G2 CLK 1 VCC I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 I/O G1 I/O G1 I/O G0 I/O G2 VCCIO VCC I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G0 I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G2 I/O G0 I/O G0 I/O G0 VCCIO VCC I/O G0 I/O G0 I/O G0 I/O G0 VCC I/O G0 I/O G0 I/O G0 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 GND NC1 NC1 NC1 VCC VCC VCCIO GND VCC I/O B1 NC1 NC1 GND GND GND GND GND GND I/O G3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4 VCCIO I/O G4 VCC I/O G4 VCCIO I/O G3 I/O G3 TOE I/O G3 I/O G3 I/O G3 I/O G3 VCC I/O G3 I/O G3 I/O G3 I/O G3 GOE 3 I/O G2 QIOCLK I/O G3 VCCIO 3 VCC I/O G2 I/O G2 SET/ I/O G2 RESET GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O G2 I/O G2 I/O G2 I/O G2 I/O G2 VCC I/O G2 I/O G1 I/O G2 VCCIO I/O G0 I/O G1 I/O G1 I/O G1 I/O G1 VCC ispLSI 8600V Bottom View VCC VCCIO I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G2 I/O G1 I/O G0 I/O G0 I/O G0 I/O G1 NC1 NC1 VCCIO GND NC1 NC1 I/O G0 I/O G0 I/O G0 I/O G0 VCC VCC GND I/O B0 I/O G0 I/O G0 I/O G0 I/O G0 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 GND VCCIO NC1 NC1 VCCIO VCC CLKEN GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 VCC VCCIO I/O B0 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 I/O B4 I/O B4 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 CLK 0 NC1 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 TMS I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 I/O B4 NC1 NC1 I/O B3 I/O B3 I/O B3 NC1 I/O B0 I/O B0 NC1 NC1 I/O B3 I/O B3 I/O B3 I/O B3 QIOCLK I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 I/O B0 NC1 I/O B3 I/O B3 I/O B3 GOE 0 I/O B2 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 TDI 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. NC pins are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 25 Specifications ispLSI 8600V Part Number Description ispLSI 8600V - XXX Device Family Device Number Speed 125 = 125 MHz fmax 90 = 90 MHz fmax 60 = 60 MHz fmax X XXXX X Grade Blank = Commercial Package B272 = 272-Ball BGA B492 = 492-Ball BGA Power L = Low 0212/8600V Ordering Information COMMERCIAL FAMILY fmax (MHz) 125 125 ispLSI 90 90 60 60 tpd (ns) 8.5 8.5 10 10 15 15 ORDERING NUMBER ispLSI 8600V-125LB272 ispLSI 8600V-125LB492 ispLSI 8600V-90LB272 ispLSI 8600V-90LB492 ispLSI 8600V-60LB272 ispLSI 8600V-60LB492 PACKAGE 272-Ball BGA 492-Ball BGA 272-Ball BGA 492-Ball BGA 272-Ball BGA 492-Ball BGA Table 2-0041/8600V 26