CIC-FILT-X2-U2

Cascaded Integrator-Comb (CIC) Filter User’s Guide August 2010 IPUG42_02.6 Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 8 Chapter 2. Functional Description ........................................................................................................ 9 Interfacing with the CIC Filter.............................................................................................................................. 10 Signal Descriptions ............................................................................................................................................. 12 Timing Diagrams ................................................................................................................................................. 13 Decimator Timing ....................................................................................................................................... 13 Interpolator Timing .............................................................................................................................................. 15 Chapter 3. Parameter Settings ............................................................................................................ 18 CIC Parameter Tab ............................................................................................................................................. 18 Parameter Descriptions....................................................................................................................................... 19 Filter Type .................................................................................................................................................. 19 Options....................................................................................................................................................... 19 Differential Delay........................................................................................................................................ 19 Decimation/Interpolation Rates .................................................................................................................. 20 Memory Type ............................................................................................................................................. 20 Optional Port .............................................................................................................................................. 20 Chapter 4. IP Core Generation............................................................................................................. 21 Licensing the IP Core.......................................................................................................................................... 21 Getting Started .................................................................................................................................................... 21 IPexpress-Created Files and Top Level Directory Structure............................................................................... 23 Instantiating the Core .......................................................................................................................................... 25 Running Functional Simulation ........................................................................................................................... 25 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 25 Hardware Evaluation........................................................................................................................................... 26 Enabling Hardware Evaluation in Diamond................................................................................................ 26 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 26 Updating/Regenerating the IP Core .................................................................................................................... 26 Regenerating an IP Core in Diamond ........................................................................................................ 26 Regenerating an IP Core in ispLEVER ...................................................................................................... 27 Chapter 5. Support Resources ............................................................................................................ 28 Lattice Technical Support.................................................................................................................................... 28 Online Forums............................................................................................................................................ 28 Telephone Support Hotline ........................................................................................................................ 28 E-mail Support ........................................................................................................................................... 28 Local Support ............................................................................................................................................. 28 Internet ....................................................................................................................................................... 28 References.......................................................................................................................................................... 28 LatticeECP/EC ........................................................................................................................................... 28 LatticeECP2M ............................................................................................................................................ 28 LatticeECP3 ............................................................................................................................................... 28 LatticeSC/M................................................................................................................................................ 29 LatticeXP.................................................................................................................................................... 29 LatticeXP2.................................................................................................................................................. 29 Revision History .................................................................................................................................................. 29 Appendix A. Resource Utilization ....................................................................................................... 30 LatticeECP and LatticeEC FPGAs ...................................................................................................................... 30 Ordering Part Number................................................................................................................................ 30 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG42_02.6, August 2010 2 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Table of Contents LatticeECP2 Devices .......................................................................................................................................... 31 Ordering Part Number................................................................................................................................ 31 LatticeECP2M Devices ....................................................................................................................................... 31 Ordering Part Number................................................................................................................................ 31 LatticeECP3 Devices .......................................................................................................................................... 32 Ordering Part Number................................................................................................................................ 32 LatticeSC/SCM Devices...................................................................................................................................... 32 Ordering Part Number................................................................................................................................ 32 LatticeXP Devices ............................................................................................................................................... 33 Ordering Part Number................................................................................................................................ 33 LatticeXP2 Devices ............................................................................................................................................. 33 Ordering Part Number................................................................................................................................ 33 IPUG42_02.6, August 2010 3 Cascaded Integrator-Comb (CIC) Filter User’s Guide Chapter 1: Introduction Cascaded Integrator-Comb (CIC) filters, also known as Hogenauer filters, are used to achieve arbitrary and large sample rate changes in digital systems. These filters are used as decimation or interpolation filters and can be efficiently implemented without multipliers, utilizing only adders and subtractors. A CIC filter is typically used in applications where the system sample rate is much larger than the bandwidth occupied by the signal. They are commonly used to build Digital Down Converters (DDCs) and Digital Up Converters (DUCs). Some applications that use the CIC filter include software design radios, cable modems, satellite receivers, 3G base stations, and radar systems. Lattice provides a widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters. Quick Facts Table 1-1 through Table 1-8 give quick facts about the CIC Filter IP core for LatticeECP™, LatticeECP2™, LattceECP2M™, LatticeECP3™, LattticeSC™, LatticeSCM™, LatticeXP™, and LatticeXP2™ devices. Table 1-1. CIC Filter IP Core for LatticeECP Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Minimal Device Needed LUTs sysMEM EBRs Registers LFEC1E Synthesis LFEC3E 218 1514 878 0 0 0 1253 1982 301 Diamond® 1.0 or ispLEVER® 8.1 Synopsys® Synplify Pro® for Lattice D-2009.12L-1 Aldec® Active-HDL® 8.2 Lattice Edition Simulation IPUG42_02.6, August 2010 LFEC3E LFECP33E-5F672C Lattice Implementation Design Tool Support Interpolator with rate is 35 and data with is 15 and stage is 7 Lattice ECP Targeted Device Resource Utilization Decimator with rate is 4096 and data with is 16 and stage is 8 Mentor Graphics® ModelSim® SE 6.3F 4 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Introduction Table 1-2. CIC Filter IP Core for LatticeECP2 Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Minimal Device Needed LUTs sysMEM EBRs Registers LFE2-6E LFE2-50E-7F672C 221 1594 985 0 0 0 301 1253 1982 Lattice Implementation Design Tool Support Interpolator with rate is 35 and data with is 15 and stage is 7 Lattice ECP2 Targeted Device Resource Utilization Decimator with rate is 4096 and data with is 16 and stage is 8 Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor ModelSim SE 6.3F Table 1-3. CIC Filter IP Core for LatticeECP2M Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported LFE2M20E Targeted Device Resource Utilization sysMEM EBRs Registers LFE2M35E-7F672C 221 1594 985 0 0 0 301 1253 1982 Lattice Implementation Design Tool Support Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation IPUG42_02.6, August 2010 Interpolator with rate is 35 and data with is 15 and stage is 7 Lattice ECP2M Minimal Device Needed LUTs Decimator with rate is 4096 and data with is 16 and stage is 8 Mentor ModelSim SE 6.3F 5 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Introduction Table 1-4. CIC Filter IP Core for LatticeECP3 Devices Quick Facts CIC IP Configuration Decimator with rate is 4096 and data with is 16 and stage is 8 Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Lattice ECP3 Minimal Device Needed LFE3-35EA Targeted Device Resource Utilization LUTs sysMEM EBRs Registers LFE3-95E-8FN672CES 220 1593 983 0 0 0 301 1253 1982 Lattice Implementation Design Tool Support Interpolator with rate is 35 and data with is 15 and stage is 7 Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor ModelSim SE 6.3F Table 1-5. CIC Filter IP Core for LatticeSC Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Minimal Device Needed LUTs sysMEM EBRs Registers LFSC3GA15E LFSC3GA25E-7F900C 212 1509 887 0 0 0 1256 1987 301 Lattice Implementation Design Tool Support Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation IPUG42_02.6, August 2010 Interpolator with rate is 35 and data with is 15 and stage is 7 Lattice SC Targeted Device Resource Utilization Decimator with rate is 4096 and data with is 16 and stage is 8 Mentor ModelSim SE 6.3F 6 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Introduction Table 1-6. CIC Filter IP Core for LatticeSCM Devices Quick Facts CIC IP Configuration Decimator with rate is 4096 and data with is 16 and stage is 8 Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Lattice SCM Minimal Device Needed LFSCM3GA15EP1 Targeted Device Resource Utilization LUTs sysMEM EBRs Registers LFSCM3GA25EP1-7F900C 212 1509 887 0 0 0 301 1256 1987 Lattice Implementation Design Tool Support Interpolator with rate is 35 and data with is 15 and stage is 7 Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor ModelSim SE 6.3F Table 1-7. CIC Filter IP Core for LatticeXP Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported LFXP3E Targeted Device Resource Utilization sysMEM EBRs Registers LFXP20E-5F484C 218 1514 878 0 0 0 301 1253 1982 Lattice Implementation Design Tool Support Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation IPUG42_02.6, August 2010 Interpolator with rate is 35 and data with is 15 and stage is 7 Lattice XP Minimal Device Needed LUTs Decimator with rate is 4096 and data with is 16 and stage is 8 Mentor ModelSim SE 6.3F 7 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Introduction Table 1-8. CIC Filter IP Core for LatticeXP2 Devices Quick Facts CIC IP Configuration Decimator with rate is 48 and data with is 8 and stage is 4 Core Requirements FPGA Families Supported Lattice XP2 Minimal Device Needed LFXP2-5E Targeted Device Resource Utilization LUTs sysMEM EBRs Registers Interpolator with rate is 35 and data with is 15 and stage is 7 LFXP2-17E-7F484C 221 1594 985 0 0 0 301 1253 1982 Lattice Implementation Design Tool Support Decimator with rate is 4096 and data with is 16 and stage is 8 Diamond 1.0 or ispLEVER 8.1 Synthesis Synopsys Synplify Pro for Lattice D-2009.12L-1 Aldec Active-HDL 8.2 Lattice Edition Simulation Mentor ModelSim SE 6.3F Features • 1-32-bit input data width • 1-8 cascaded stages • 1-4 cycles differential delay, run-time programmable for both decimation and interpolation • 2-16,384 decimation and interpolation sampling rate factor, run-time programmable rates for both decimation and interpolation • Multi-channel (up to 40 channels) support for both decimation and interpolation • Fully synchronous, single-clock design IPUG42_02.6, August 2010 8 Cascaded Integrator-Comb (CIC) Filter User’s Guide Chapter 2: Functional Description This chapter provides a functional description of Lattice's CIC Filter IP core. Figure 2-1 shows a top-level inteface diagram for the CIC Filter. Figure 2-1. Top-level Interface Diagram for CIC Filter clk ce rstn clear dout din outvalid CIC Filter inpvalid ibstart obstart rfi firdf firdfset rate rateset A CIC filter is constructed using two kinds of blocks: an integrator and a comb. An integrator is a single-pole IIR filter with a unity feedback coefficient operating at a higher sampling rate, fS. A comb is a FIR filter with M unity differential delays operating at a lower sampling rate, fS/R, where M and R are integers. The main features of the integrator and the comb are summarized in Table 2-1. Table 2-1. Main Features of Integrator and Comb Feature Integrator Z Structure Comb -1 Z + x(n) + -M - + y(n) x(n) + + fs fs/R y[n] y[n-1] + x[n] x[n] -x[n-RM] HI(z) 1 1 - z-1 1 - z-RM 1 2(1 - cosω) 2(1 - cos RM) Sampling Rate |H(ejw)|2 IPUG42_02.6, August 2010 9 y(n) Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description A CIC decimator and interpolator with N stages are shown in Figure 2-2, where I and C represent an integrator and a comb, respectively. The symbols, R and R, represent down-sampling and up-sampling, respectively. Figure 2-2. CIC Decimator and Interpolator (a) CIC Decimator x(n) I I I R C N Stages C C y(n) I y(n) N Stages (b) CIC Interpolator x(n) C C C R I N Stages I N Stages The system transfer function of the CIC decimator and interpolator in the z-plane is H(z) = (1 - z-RM)N = (1 - z-1)N N RM-1 z -k (1) k=0 The frequency response can be derived by substituting z=j2¼f in Equation 1, where f is the frequency relative to the low sampling rate, fS/R. sinMf H(f) = f sin R N (2) By using sin xÝx for small x, we can approximate Equation 2 for a large R as N N sinMf sinMf H(f) = = RM = [RMsinc(Mf)]N if f 1) ibstart 1 H I Input Block Start. Indicates that the first valid data of an input data cycle is being presented at the input port din. obstart 1 H O Output Block Start. Indicates that output port dout contains a valid sample for the first channel. IPUG42_02.6, August 2010 12 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description Table 2-2. Interface Signal Descriptions (Continued) Name Bits Active I/O Description Programmable Sampling Rate Mode Only (when Programmable delay = “Yes”) rate rateset 2 to 145 — I Sampling Rate. This port is used for feeding the dynamic sampling rate factor of the CIC filter. The width of this port is equal to the next higher integer value of log2 (Max rate +1). 1 H I Set Sampling Rate. Indicates that input port rate contains a valid rate factor. Programmable Differential Delay Mode Only (when Programmable rate = “Yes”) firdf firdfset 1 or 3 — I Differential Delay. This port is used for feeding the dynamic differential delay of the FIR stages. The width of this port is equal to the next higher integer value of log2 (Max delay +1). 1 H I Set Differential Delay. Indicates that input port firdf contains a valid differential delay factor. Other Optional Ports ce 1 H I Clock Enable. This signal has the highest priority after rstn. The CIC filter operation halts as long as ce is held low. Choosing this option will increase resource utilization. Available only if Clock enable is selected. clear 1 H I System Clear. The optional signal ce, if used, must be held high for clear to be effective. Choosing this option will increase resource utilization. Available only if System clear is selected. Timing Diagrams Decimator Timing Interface timing for four cases of decimators are presented in Figure 2-3 and a brief description of each case is given below. The down-sampling rate is equal to 2 (Rate = 2) for all cases described. • Figure 2-3(a): A new input sample is available at every clock cycle in a continuous manner, so inpvalid signal is continuously held high. There is one valid output for every Rate clock cycles, as indicated by the outvalid signal. • Figure 2-3(b): A new input sample is available once in every two clock cycles in an intermittent manner. As one input is given for every two clock cycles, there is one valid output for every four (2*Rate) clock cycles, as indicated by the outvalid signal. • Figure 2-3(c): Interlaced dual-channel input samples x and u are supplied in every clock cycle in a continuous manner, so ibstart signal is high during the first channel sample x input. For the second channel sample u, ibstart must be low. Inpvalid is high for each valid input sample. After a few clock cycles of the first input sample to the IP core, the outvalid signal will be asserted for each valid output data. The signal obstart indicates data for the first channel. Then, subsequent output samples for each channel will be available every 2*Rate clock cycles. • Figure 2-3(d): Interlaced dual-channel input samples x and u are supplied in every two-clock clock cycles in an intermittent manner. After a few clock cycles of the first input sample to the IP core, the outvalid signal will be asserted for each valid output data. The signal obstart indicates data for the first data. Then, subsequent output samples for each channel will be available every 4*Rate clock cycles. IPUG42_02.6, August 2010 13 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description Figure 2-3. CIC Decimator Timing Diagrams (a) Single-Channel: Inputs are sampled in every clock cycle: clk din x(0) x(1) x(2) x(3) x(4) x(5) x(6) x(7) x(8) x(9) x(10) x(11) x(12) x(13) x(14) x(15) x(16) x(17) x(18) x(19) inpvalid dout y(0) y(1) y(2) y(3) y(4) y(5) y(6) outvalid Filter Latency + Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles x(6) x(7) Rate Clock Cycles (b) Single-Channel: Inputs are sampled in every two-clock cycle: clk din x(0) x(1) x(2) x(3) x(4) x(5) x(8) x(9) inpvalid dout y(0) y(1) y(2) outvalid Filter Latency + 2* Rate Clock Cycles 2* Rate Clock Cycles 2* Rate Clock Cycles (c) Dual-Channel: Inputs are sampled in every clock cycle: clk din x(0) u(0) x(1) u(1) x(2) u(2) x(3) u(3) x(4) yx (0) yu (0) u(4) x(5) u(5) x(6) yx (1) yu (1) u(6) x(7) u(7) x(8) yx (2) yu(2) u(8) x(9) ibstart inpvalid dout obstart outvalid Filter Latency + 2* Rate Clock Cycles Clock Cycles IPUG42_02.6, August 2010 2* Rate Clock Cycles 14 2* Rate Clock Cycles 2* Rate Clock Cycles Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description (d) Dual-Channel: Inputs are sampled in every two clock cycles: clk din x(0) u(0) x(1) u(1) x(2) u(2) x(3) u(3) x(4) u(4) ibstart inpvalid yx (0) dout yu (0) y x(1) y u (1) obstart outvalid Filter Latency + 4* Rate Clock Cycles 4* Rate Clock Cycles Interpolator Timing The interface timing for four cases of interpolators are presented in Figure 2-4 and a brief description of each case is given below. The up-sampling rate is equal to 2 (Rate = 2) for all cases described. • Figure 2-3(a): A new input sample is available in every Rate clock cycles, so inpvalid signal during those cycles. The CIC will activate the rfi signal when it is ready to read the next sample. When rfi is inactive, the CIC cannot accept a new input sample in the next clock cycle. The output samples are available continuously, after the initial latency. • Figure 2-3(b): A new input sample is available in every 2*Rate clock cycles. The IP core will deactivate the rfi signal for (Rate - 1) clock cycles when a sample is inputted. When rfi is inactive, IP core cannot accept a new input sample in the next clock cycle. After a few clock cycles of the first input sample to the IP core, the  outvalid signal will be asserted for Rate clock cycles to indicate the output samples interpolated from the first input sample are available. Then, subsequent output samples will be available for Rate clock cycles in every 2*Rate clock cycles intermittently. • Figure 2-3(c): Interlaced dual-channel input samples x and u are supplied in every 2*Rate clock cycles, so ibstart signal is high in every Rate clock cycles during the first channel sample x input. The IP core will deactivate rfi signal for 2*(Rate - 1) clock cycles happened before the last channel input. When rfi is inactive, IP core cannot accept a new block of input samples in the next clock cycle. After a few clock cycles of the first input sample to the IP core, the outvalid signal will be asserted to indicate the output sample yx for x and yu for u are available. The signal obstart indicates data for the first channel. Then, subsequent output samples will be available continuously. • Figure 2-3(d): Interlaced dual-channel input samples x and u are supplied in every 4*Rate clock cycles. The IP core will deactivate the rfi signal for 2*(Rate - 1) clock cycles before the last channel input. When rfi is inactive, the IP core cannot accept a new input sample in the next clock cycles. After a few clock cycles of the first input sample to the IP core, the outvalid signal will be asserted to indicate the output sample yx for x and yu for u are available. The signal obstart indicates data for the first channel. Then, subsequent output samples will be available for 2*Rate clock cycles in every 4*Rate clock cycles intermittently. IPUG42_02.6, August 2010 15 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description Figure 2-4. CIC Interpolator Timing Diagrams (a) Single-Channel: Inputs are sampled in every Rate clock cycles: clk din x(0) x(1) x(2) x(3) x(4) x(5) x(6) x(7) x(8) x(9) inpvalid rfi y(0) dout y(1) y(2) y(3) y(4) y(5) y(6) y(7) y(8) y(9) y(10) y(11) y(12) outvalid Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Rate Clock Cycles Filter Latency + Rate Clock Cycles (b) Single-Channel: Inputs are sampled in every 2*Rate clock cycles: clk din x(0) x(1) x(2) x(3) x(4) inpvalid rfi dout y(0) y(1) y(2) y(3) y(4) y(5) outvalid 2* Rate Clock Cycles 2* Rate Clock Cycles 2* Rate Clock Cycles 2* Rate Clock Cycles Filter Latency + 2* Rate Clock Cycles IPUG42_02.6, August 2010 16 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Functional Description (c) Dual-Channel: Inputs are sampled in every Rate clock cycles: clk din x(0) u(0) x(1) u(1) x(2) u(2) y x(0) y u(0) x(3) u(3) y x(2) y u(2) x(4) u(4) ibstart ibstart rfib dout y x(1) y u(1) y x(3) y u(3) y x(4) y u (4) y x (5) obstart outvalid 2* Rate Clock Cycles 2* Rate Clock Cycles 2* Rate Clock Cycles 2* Rate Clock Cycles Filter Latency+ 2* Rate Clock Cycles (d) Dual-Channel: Inputs are sampled in every 2*Rate clock cycles: clk din x(0) u(0) x(1) u(1) y x(0) y u(0) x(1) u(1) y x(2) y u (2) ibstart inpvalid rfi dout y x(1) y u(1) y x(3) y obstart outvalid 4* Rate Clock Cycles 4* Rate Clock Cycles Filter Latency+ 4* Rate Clock Cycles IPUG42_02.6, August 2010 17 Cascaded Integrator-Comb (CIC) Filter User’s Guide Chapter 3: Parameter Settings The IPexpress™ tool is used to create IP and architectural modules in the Diamond or ispLEVER software. Refer to “IP Core Generation” on page 21 for a description on how to generate the IP. Table 3-1 provides the list of user configurable parameters for the CIC Filter IP core. The parameter settings are specified using the CIC Parameter Tab in IPexpress. Table 3-1. CIC Filter IP Core Configuration Parameters Parameter Range/Options Default Decimator, Interpolator Decimator Filter Type Filter type Options Input data width 1 to 32 bits 8 bits Stages 1 to 8 4 Number of channels 1 to 40 1 Differential Delay Programmable delay Yes, No No Delay 1 to 4 1 Max delay 2 to 4 2 Decimation/Interpolation Rates Programmable rate Yes, No No Rate 2 to 16384 48 Max rate 4 to 16384 64 Min rate 2 to 8 2 Distributed, EBR Distributed System clear Yes, No No Clock enable Yes, No No Memory Type Memory Type Optional Port CIC Parameter Tab Figure 3-1 shows the Parameter Tab.. IPUG42_02.6, August 2010 18 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Parameter Settings Figure 3-1. CIC Parameter Tab Parameter Descriptions This section describes the available parameters for the CIC Filter IP core. Filter Type This parameter determines whether the CIC filter is configured as an interpolator or a decimator. Options Input Data Width This parameter specifies the width of the input data in bits. Stages This parameter specifies the number of integrator and comb stages. Number of Channels This parameter specifies the number of time-shared data channels. Differential Delay Programmable Delay This parameter determines whether the differential delay is fixed or programmable. When Programmable delay is selected, ports firdf and firdfset will be added. Delay This parameter is only available when Programmable delay is not selected. This parameter sets the differential delay factor in each FIR filter. Max Delay IPUG42_02.6, August 2010 19 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Parameter Settings This parameter is only available when Programmable delay is selected. This parameter specifies the max differential delay factor in each FIR filter. Decimation/Interpolation Rates Programmable Rate This parameter determines whether the sampling rate is fixed or programmable. When Programmable rate is selected, ports rate and rateset will be added. Rate This parameter is only available when Programmable rate is not selected. This parameter specifies down-sampling or up-sampling rate. Max Rate This parameter is only available when Programmable rate is selected. This parameter specifies the maximum value for the down-sampling or the up-sampling rate. Min Rate This parameter is only available when Programmable rate is selected. This parameter specifies the minimum down-sampling or up-sampling rate. Note that more logic resources will be used as a smaller Min rate is selected. Memory Type Memory Type This parameter indicates which type of memory is used in the core, distributed (LUT-based) or EBR. Optional Port System Clear This parameter determines whether the system clear port clear is present. Clock Enable This parameter determines whether the clock enable port ce is present. IPUG42_02.6, August 2010 20 Cascaded Integrator-Comb (CIC) Filter User’s Guide Chapter 4: IP Core Generation This chapter provides information on how to generate the CIC Filter IP core using the Diamond or ispLEVER software IPexpress tool, and how to include the core in a top-level design. Licensing the IP Core An IP core- and device-specific license is required to enable full, unrestricted use of the CIC Filter IP core in a complete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at: http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm Users may download and generate the CIC Filter IP core and fully evaluate the core through functional simulation and implementation (synthesis, map, place and route) without an IP license. The CIC Filter IP core also supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited time (approximately four hours) without requiring an IP license. See “Hardware Evaluation” on page 26 for further details. However, a license is required to enable timing simulation, to open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout limitation. Getting Started The CIC Filter IP core is available for download from the Lattice IP Server using the IPexpress tool. The IP files are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP core has been installed, the IP core will be available in the IPexpress GUI dialog box shown in Figure 4-1. The IPexpress tool GUI dialog box for the CIC Filter IP core is shown in Figure 4-1. To generate a specific IP core configuration the user specifies: • Project Path – Path to the directory where the generated IP files will be loaded. • File Name – “username” designation given to the generated IP core and corresponding folders and files. • (Diamond) Module Output – Verilog or VHDL. • (ispLEVER) Design Entry Type – Verilog HDL or VHDL. • Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3, etc.). Only families that support the particular IP core are listed. • Part Name – Specific targeted part within the selected device family. IPUG42_02.6, August 2010 21 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation Figure 4-1. IPexpress Dialog Box (Diamond Version) Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display the CIC Filter IP core Configuration GUI, as shown in Figure 4-2. From this dialog box, the user can select the IP parameter options specific to their application. Refer to “Parameter Settings” on page 18 for more information on the CIC Filter IP core parameter settings. IPUG42_02.6, August 2010 22 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation Figure 4-2. Configuration Dialog Box (Diamond Version) IPexpress-Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3. IPUG42_02.6, August 2010 23 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation Figure 4-3. LatticeECP3 CIC Filter IP Core Directory Structure Table 4-1 provides a list of key files created by the IPexpress tool and how they are used. The IPexpress tool creates several files that are used throughout the design cycle. The names of most of the created files are customized to the user’s module name specified in the IPexpress tool.t Table 4-1. File List File Description _inst.v This file provides an instance template for the IP. _bb.v This file provides the synthesis black box for the user’s synthesis. .ngo The ngo files provide the synthesized IP core. .ipx The IPX file holds references to all of the elements of an IP or Module after it is generated from the IPexpress tool (Diamond version only). The file is used to bring in the appropriate files during the design implementation and analysis. It is also used to re-load parameter settings into the IP/Module generation GUI when an IP/Module is being re-generated. .lpc This file contains the IPexpress tool options used to recreate or modify the core in the IPexpress tool. _top.[v,vhd] This file provides a module which instantiates the CIC IP core. This file can be easily modified for the user's instance of the CIC IP core. This file is located in the cic_filter_eval//src/rtl/top/ directory. _generate.tcl Created when the GUI Generate button is pushed, this file invokes generation, may be run from command line. _generate.log This is the IPexpress scripts log file. _gen.log This is the IPexpress IP generation log file IPUG42_02.6, August 2010 24 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation Instantiating the Core The generated CIC IP core package includes black-box (_bb.v) and instance (_inst.v) templates that can be used to instantiate the core in a top-level design. An example RTL top-level reference source file that can be used as an instantiation template for the IP core is provided in  \\cic_filter_eval\\src\rtl\top. Users may also use this top-level reference as the starting template for the top-level for their complete design. Running Functional Simulation Simulation support for the CIC IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator and Mentor Graphics ModelSim simulator. The functional simulation includes a configuration-specific behavioral model of the CIC IP core. The test bench sources stimulus to the core, and monitors output from the core. The generated IP core package includes the configuration-specific behavior model (_beh.v) for functional simulation in the “Project Path” root directory. The simulation scripts supporting ModelSim evaluation simulation is provided in \\cic_filter_eval\\sim\modelsim\scripts. The simulation script supporting Aldec evaluation simulation is provided in \\cic_filter_eval\\sim\aldec\scripts. Both ModelSim and Aldec simulation is supported via test bench files provided in  \\cic_filter_eval\testbench. Models required for simulation are provided in the corresponding \models folder. Users may run the Aldec evaluation simulation by doing the following: 1. Open Active-HDL. 2. Under the Tools tab, select Execute Macro. 3. Browse to folder \\cic_filter_eval\\sim\aldec\scripts and execute one of the “do” scripts shown. Users may run the ModelSim evaluation simulation by doing the following: 1. Open ModelSim. 2. Under the File tab, select Change Directory and choose the folder \cic_filter_eval\\sim\modelsim\scripts. 3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown. Note: When the simulation completes, a pop-up window will appear asking “Are you sure you want to finish?” Answer No to analyze the results. (Answering Yes closes ModelSim). Synthesizing and Implementing the Core in a Top-Level Design Synthesis support for the CIC IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The CIC IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress. Users may synthesize the core in their own top-level design by instantiating the core in their top-level as described previously and then synthesizing the entire design with either Synplify or Precision RTL Synthesis. The following text describes the evaluation implementation flow for Windows platforms. The flow for Linux and UNIX platforms is described in the Readme file included with the IP core. The top-level files _top.v is provided in \\cic_filter_eval\\src\rtl\top. Push-button implementation of the reference design is supported via Diamond or ispLEVER project files, .syn, located in the following directory: \\cic_filter_eval\\impl\(synplify or precision). To use this project file in Diamond: 1. Choose File > Open > Project. IPUG42_02.6, August 2010 25 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation 2. Browse to  \\cic_filter_eval\\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open .ldf. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project. 4. Select the Process tab in the left-hand GUI window. 5. Implement the complete design via the standard Diamond GUI flow. To use this project file in ispLEVER: 1. Choose File > Open Project. 2. Browse to  \\cic_filter_eval\\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open .syn. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project. 4. Select the device top-level entry in the left-hand GUI window. 5. Implement the complete design via the standard ispLEVER GUI flow. Hardware Evaluation The CIC Filter IP core supports supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Enabling Hardware Evaluation in Diamond Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be enabled/disabled in the Strategy dialog box. It is enabled by default. Enabling Hardware Evaluation in ispLEVER In the Processes for Current Source pane, right-click the Build Database process and choose Properties from the dropdown menu. The hardware evaluation capability may be enabled/disabled in the Properties dialog box. It is enabled by default. Updating/Regenerating the IP Core By regenerating an IP core with the IPexpress tool, you can modify any of its settings including device type, design entry method, and any of the options specific to the IP core. Regenerating can be done to modify an existing IP core or to create a new but similar one. Regenerating an IP Core in Diamond To regenerate an IP core in Diamond: 1. In IPexpress, click the Regenerate button. 2. In the Regenerate view of IPexpress, choose the IPX source file of the module or IP you wish to regenerate. 3. IPexpress shows the current settings for the module or IP in the Source box. Make your new settings in the Target box. IPUG42_02.6, August 2010 26 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor IP Core Generation 4. If you want to generate a new set of files in a new location, set the new location in the IPX Target File box. The base of the file name will be the base of all the new file names. The IPX Target File must end with an .ipx extension. 5. Click Regenerate. The module’s dialog box opens showing the current option settings. 6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the About tab in IPexpress for links to technical notes and user guides. IP may come with additional information. As the options change, the schematic diagram of the module changes to show the I/O and the device resources the module will need. 7. To import the module into your project, if it’s not already there, select Import IPX to Diamond Project (not available in stand-alone mode). 8. Click Generate. 9. Check the Generate Log tab to check for warnings and error messages. 10.Click Close. The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP core required to support simulation, synthesis and implementation. The IP core may be included in a user's design by importing the .ipx file to the associated Diamond project. To change the option settings of a module or IP that is already in a design project, double-click the module’s .ipx file in the File List view. This opens IPexpress and the module’s dialog box showing the current option settings. Then go to step 6 above. Regenerating an IP Core in ispLEVER To regenerate an IP core in ispLEVER: 1. In the IPexpress tool, choose Tools > Regenerate IP/Module. 2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. 4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension. 5. Click Next. The IP core’s dialog box opens showing the current option settings. 6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG42_02.6, August 2010 27 Cascaded Integrator-Comb (CIC) Filter User’s Guide Chapter 5: Support Resources This chapter contains information about Lattice Technical Support, additional references, and document revision history. Lattice Technical Support There are a number of ways to receive technical support. Online Forums The first place to look is Lattice Forums (http://www.latticesemi.com/support/forums.cfm). Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers. Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m. Pacific Time. • For USA & Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • techsupport@latticesemi.com • techsupport-asia@latticesemi.com Local Support Contact your nearest Lattice Sales Office. Internet www.latticesemi.com References • An Economical Class of Digital Filter for Decimation and Interpolation, Eugene B. Hogenauer, IEEE. Trans. ASSP, Vol. 29, No. 2, pp.155-162, April 1981. • CIC Filter Introduction, Matthew P. Donadio, Iowegian, www.users.snip.net/~donadio/cic.pdf. LatticeECP/EC • HB1000, LatticeECP/EC Family Handbook LatticeECP2M • HB1003, LatticeECP2M Family Handbook LatticeECP3 • HB1009, LatticeECP3 Family Handbook IPUG42_02.6, August 2010 28 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Support Resources LatticeSC/M • DS1004, LatticeSC/M Family Data Sheet LatticeXP • HB1001, LatticeXP Family Handbook LatticeXP2 • DS1009, Lattice XP2 Data Sheet Revision History Document Version IP Version — — 2.0 Previous Lattice releases. September 2006 02.1 2.1 Added IPexpress User-Configurable Core section. Date Change Summary Updated LatticeECP/EC appendix. Added LatticeECP2, LatticeSC and LatticeXP appendices. December 2006 May 2007 02.2 2.2 Updated appendices. Added support for LatticeECP2M device family. 02.3 2.3 Added support for LatticeXP2 FPGA family. Updated LatticeXP and LatticeECP2M appendices. November 2008 02.4 2.4 Updated appendices. July 2010 02.5 3.0 Divided document into chapters. Added table of contents. Updated content for 3.0 version of IP core Added Quick Facts tables in Chapter 1, “Introduction.” Added new content in Chapter 3, “Parameter Settings.” Added new content in Chapter 4, “IP Core Generation.” August 2010 2.6 IPUG42_02.6, August 2010 3.1 Added support for Diamond software throughout. 29 Cascaded Integrator-Comb (CIC) Filter User’s Guide Appendix A: Resource Utilization This appendix gives resource utilization information for Lattice FPGAs using the CIC Filter IP core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com/software. LatticeECP and LatticeEC FPGAs Table A-1. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM™ EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 166 216 301 0 212 Decimator, 16-bit data, 8 stages, 1 channel 837 1509 1253 0 109 Interpolator, 15-bit data, 7 stages, 4 channels 1205 898 1980 0 160 1. Performance and utilization data are generated using an LFECP33E-5F672C device, with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeECP/EC devices is CIC-FILTRE2-U2. Table A-2 lists the parameter settings that are available for the CIC. Table A-2. Parameter Settings of the Standard Configurations Parameter Name Config 1 Config 2 Config 3 No No Yes ARC_INW 8 16 15 ARC_STAGE 4 8 7 ARC_INTERPOLATOR ARC_CHANNEL PROG_FIRDF ARC_FIRDF 1 1 4 No No No 1 2 4 No No No ARC_RATE=35 48 4096 35 PORT_CLEAR=No No No No PROG_RATE=No PORT_CE=No No No No PORT_CHOUT=No No No No PORT_OBSTART=No No No No PORT_RFI=No No No No 2 2 2 ARC_RATE_MIN=2 IPUG42_02.6, August 2010 30 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Resource Utilization LatticeECP2 Devices Table A-3. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 168 219 301 0 272 Decimator, 16-bit data, 8 stages, 1 channel 878 1589 1253 0 144 Interpolator, 15-bit data, 7 stages, 4 channels 1238 985 1980 0 230 1. Performance and utilization data are generated using an LFE2-50E-7F672C device, with Lattice Diamond 1.0 and Synplify Pro D-2009.12L1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeECP2 devices is CIC-FILTR-P2U2. Table A-2 lists the parameter settings that are available for the CIC. LatticeECP2M Devices Table A-4. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 168 219 301 0 284 Decimator, 16-bit data, 8 stages, 1 channel 878 1589 1253 0 143 Interpolator, 15-bit data, 7 stages, 4 channels 1238 985 1980 0 234 1. Performance and utilization data are generated using an LFE2M-35E-7F672C device, with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeECP2M devices is CIC-FILTRPM-U2. Table A-2 lists the parameter settings that are available for the CIC. IPUG42_02.6, August 2010 31 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Resource Utilization LatticeECP3 Devices Table A-5. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMHz (MHz) Decimator, 8-bit data, 4 stages, 1 channel 167 218 301 0 320 Decimator, 16-bit data, 8 stages, 1 channel 873 1588 1253 0 145 Interpolator, 15-bit data, 7 stages, 4 channels 1216 983 1980 0 237 1. Performance and utilization data are generated using an LFE3-95E-8FN672CES device, with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeECP3 devices is CIC-FILT-E3U2. Table A-2 lists the parameter settings that are available for the CIC. LatticeSC/SCM Devices Table A-6. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 163 212 301 0 397 Decimator, 16-bit data, 8 stages, 1 channel 839 1510 1259 0 202 Interpolator, 15-bit data, 7 stages, 4 channels 1162 887 1981 0 284 1. Performance and utilization data are generated using an LFSC3GA25E-7F900C device, with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeSC devices is CIC-FILTR-SCU2. Table A-2 lists the parameter settings that are available for the CIC. IPUG42_02.6, August 2010 32 Cascaded Integrator-Comb (CIC) Filter User’s Guide Lattice Semiconductor Resource Utilization LatticeXP Devices Table A-7. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 166 216 301 0 196 Decimator, 16-bit data, 8 stages, 1 channel 837 1509 1253 0 103 Interpolator, 15-bit data, 7 stages, 4 channels 1205 898 1980 0 155 1. Performance and utilization data are generated using an LFXP20E-5F484C device, with Lattice Diamond 1.0 and Synplify Pro D-2009.12L1 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance and utilization may vary. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeXP devices is CIC-FILTR-XPU2. Table A-2 lists the parameter settings that are available for the CIC. LatticeXP2 Devices Table A-8. Performance and Resource Utilization1 IPexpress User-Configurable Mode SLICEs LUTs Registers sysMEM EBRs fMAX (MHz) Decimator, 8-bit data, 4 stages, 1 channel 168 219 301 0 285 Decimator, 16-bit data, 8 stages, 1 channel 878 1589 1253 0 152 Interpolator, 15-bit data, 7 stages, 4 channels 1238 985 1980 0 234 1. Performance and utilization data are generated using an LFXP2-17E-7F484C device, with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. Ordering Part Number The Ordering Part Number (OPN) for all configurations of the CIC targeting LatticeXP2 devices is CIC-FILTR-X2U2. Table A-2 lists the parameter settings that are available for the CIC. IPUG42_02.6, August 2010 33 Cascaded Integrator-Comb (CIC) Filter User’s Guide