DIAMOND-E-12M

ADVANCED DESIGN SOFTWARE Leading-edge design and implementation tools optimized for Lattice FPGA architectures Lattice Diamond® design software offers leading-edge design and implementation tools optimized for cost-sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER® featuring design exploration, ease of use, improved design flow, and numerous other enhancements. This combination of new and enhanced features allows users to complete designs faster, easier and with better results than before. Diamond software is available as a download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either a free license or a subscription license. Diamond Software Free License A free license can be downloaded from the Lattice website. This license provides immediate access to many popular Lattice devices such as MachXO2™, MachXO™, Platform Manager 2, and LatticeXP2™ at no cost. It includes Synopsys® Synplify Pro™ for Lattice synthesis and Aldec® Active-HDL™ Lattice Edition II mixed language simulator.* Diamond Software Subscription License A subscription license provides support for all Lattice FPGAs including the Lattice ECP3 devices. It also includes Synopsys® Synplify Pro™ for Lattice synthesis and Aldec Active-HDL Lattice Edition II mixed language simulator*. *Aldec Active-HDL Lattice Edition II simulator is only available for Windows. Floating licenses require the additional ALDEC-USBKEY product. Key Features and Benefits Design Exploration • Explore design alternatives with Implementations & Strategies • Run Manager for accelerating exploration and utilizing multicore processors • Lattice Synthesis Engine (LSE) for additional synthesis exploration options. Ease-of-Use Features • Advanced next generation user interface • Report view with message filtering features • Extensive cross-probing support • File list View for managing multiple constraint, preference, debug, timing analyzer, and power calculator files • ECO Editor for specific physical netlist-level changes • Platform Designer tool for mixed signal device applications • Programmer for improved programming support Improved Design Flow • New Timing Analyzer view allows updated timing analysis, including clock jitter analysis, without re-implementing the design • Simulation Wizard to easily export designs to multiple simulators Additional Software Included with Diamond • LatticeMico™ system integration for embedded microprocessor applications • EPIC full-featured physical netlist-level editor LATTICESEMI.COM Lattice Diamond Key Features Design Exploration Projects / Implementations/ Strategies Diamond allows more robust projects and offers new capabilities for improved design exploration. Key features include: Mixing of Verilog, VHDL, EDIF, and schematic sources Implementations allow multiple versions of a design within a single project for easy design exploration Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects Manage and choose files for constraints, timing analysis, power calculation, and hardware debug Use Run Manager view for parallel processing of multiple implementations to explore design alternatives for the best results HDL Analysis Tools Hierarchy view automatically parses and displays the design structure Displays post-synthesis and post-map design resources Provides easy access to source files for each hierarchy level Options for hierarchy control, test bench generation, and symbol generation The HDL Diagram tool shows a graphical display of the design structure and provides BKM (Best Known Methods) rule checks. Synthesis Options Lattice Synthesis Engine (LSE) and Synplify Pro are available for exploring to achieve best results. LSE supports MachX O2 TM and MachXO T M , while Synplify Pro is applicable for all devices. These two synthesis options support Verilog and VHDL languages and uses Synopsys Design Compiler Constraints format for constraints. Ease of Use GUI for a New Generation of Tools The Diamond user interface combines leading edge features and customization while offering improved ease of use. All tools open in “Views” integrated into a common user interface. Once the operation for a single tool is learned, this knowledge can be applied to other tools. Key GUI Elements Common menu and button locations for all views Three user interface sections for tools, projects, and output Start Page – open projects, import ispLEVER projects, online help, software updates Report View – centralized location for all reports from implementation tools Speeding Common Functions with ECO Editor & Programmer ECO Editor provides easy editing of common netlist changes without using the EPIC full editor Programmer allows easy and intuitive programming of FPGAs Deployment Tool creates a device programming file format for the user’s deployment method Improved Design Flow Fast, Easy Timing Analysis Timing Analysis view offers an easy-touse graphical environment for navigating timing information. See timing, schematic, and detailed paths for any constraint graphically Easy visual cues provide instant design feedback Rapidly updated analysis when timing constraints are changed Add clock jitter analysis to improve the robustness of your design Scripting with Tcl Tcl command dictionaries for projects, netlists, HDL code checking, power calculation, and hardware debug In addition to the Tcl console in the Diamond environment, a separate Tcl console application allows running scripts independently Easy Export to Simulators The new Simulation Wizard guides you through all the necessary steps to get your design to Aldec or ModelSim simulators in the manner you choose. Lattice Diamond Key Tools Message Filtering Platform Designer Hierarchy View Analyze your design easily by filtering out messages once you have checked them. Messages can be filtered individually, by IDs, categories, or severity. Platform Designer is a tool for easily building mixed-signal applications using the Platform Manager II device family. Easily configure your design elements and compile even when the target is for multiple chips. In addition to showing the design hierarchy, important information is available here such as source files used, and both post-synthesis and post-map resources used. Timing Analysis Floorplan View Physical View Timing Analysis view allows interactive editing of timing constraints and analysis speeding the timing closure flow. Floorplan View provides the ability to view design placement and edit placement constraints. A detailed, read-only view of the physical routing of paths for a more detailed understanding of timing issues. Reveal Hardware Debugger Power Calculator IPexpress The Reveal Hardware Debugger uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Power Calculator uses a data driven model to provide accurate results based on actual silicon performance for both estimation and calculation. An interface to the Lattice catalog of modules and IP optimized for Lattice devices. Feature Description Power Calculator • Uses highly accurate data models and a data-driven power model • Provides power estimation and calculation results, graphical power displays, and reports • In addition, Power Estimator is a stand-alone tool that provides power estimation Spreadsheet View • Enter and view design constraints (pin assignments, clock resource usage, global preferences, timing preferences, and more) • Checks pin assignments real-time or on-demand Package View • Easy graphical assignment of signals to pins • Graphical representation of SSO noise analysis Floorplanning Tasks • Floorplan View – view design placement and edit placement constraints • Physical View – detailed view of physical routing of paths to understand timing issues • Netlist View – browse design ports, instances, and nets. Drag and drop into other views to set constraints. • NCD View – detailed usage information of physical components • Device View – view device resources and edit placement constraints Lattice Synthesis Engine (LSE) • Supports MachXO2 and MachXO device families • Supports Verilog, VHDL, and mixed HDL designs • Uses Synopsys Design Compiler (SDC) format for constraints Reveal Hardware Debugger • Easy insertion of embedded logic analyzer debug hardware for real-time analysis • New streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display IPexpress • The interface to the catalog of modules and intellectual property (IP) optimized for Lattice devices • Import a reference file for each module or IP to easily incorporate the changes resulting from regenerating a module or IP Programmer • Comprehensive device programming manager • Efficiently programs Lattice devices using JEDEC and bitstream files generated by Lattice software Deployment Tool • Creates various device programming file formats for testers, embedded systems or external memories Synopsys Synplify Pro for Lattice Synthesis • Automatically produce an RTL schematic of your design • Mixed VHDL and Verilog synthesis support • Automatic re-timing (balancing registers across combinatorial logic) Aldec Active-HDL Simulation • Mixed language simulation of VHDL and Verilog • Language Assistant • Advanced Breakpoint Management Diamond Software Configuration Summary Lattice Diamond Free License Lattice Diamond Subscription License Lattice Device Support X LatticeECP3, LatticeECP2M/S, LatticeSC™, LatticeSCM™, LatticeECP2/S MachXO2, MachXO, Platform Manager 2, Platform Manager, LatticeECP™, LatticeEC™, LatticeXP™, LatticeXP2, LatticeECP2 X X X X Synopsys Synplify Pro X X Aldec Active-HDL Lattice Edition II X X Windows 7 (64-bit app for 64-bit OS, 32-bit app for 32-bit OS), Vista and XP (32-bit app for 32-bit OS) X X Linux – REHL 6, 5 and 4; Novell SUSE 10 X X 1 Year Nodelocked Only, Renewable 1 Year Subscription, Nodelocked or Floating N/A DIAMOND-E-12M Key Software Features Complete Diamond Software Environment Third-Party Software Operating Systems Licensing and Ordering License Terms Ordering Part Number Related Products Product Description Ordering Part Number USB Key for Aldec Simulation Floating License Required to use Aldec simulation with a floating license. Existing USB keys from ispLEVER can also be used with Diamond software. ALDEC-USBKEY Download Cable (1.2V to 5V USB Programming Cable) USB programming cable HW-USBN-2A Download Cable (1.8V to 5V Parallel Port Programming Cable) Parallel port programming cable HW-DLN-3C Applications Support techsupport@latticesemi.com Copyright © 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), IPexpress, ispLEVER, ispVM, Lattice Diamond, LatticeEC, LatticeECP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeMico, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MachXO, MachXO2, Reveal and sysIO are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 2013 Order #: I0207G LATTICESEMI.COM