Scatter-Gather Direct Memory Access Controller IP Core User Guide
March 2015
IPUG67_1.8
Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ....................................................................................................................................................... 4
Chapter 2. Functional Description ........................................................................................................ 5
Key Concepts........................................................................................................................................................ 5
Block Diagram.............................................................................................................................................. 6
WISHBONE Interfaces................................................................................................................................. 6
Control and Status ....................................................................................................................................... 6
Channel Arbiter ............................................................................................................................................ 7
BDRAM Interface ......................................................................................................................................... 7
PBUFF Interface .......................................................................................................................................... 7
DMA Engine ................................................................................................................................................. 7
Buffer Status Mode ...................................................................................................................................... 8
AUXCTRL and AUXSTAT............................................................................................................................ 9
Primary I/O ................................................................................................................................................... 9
System Configurations ............................................................................................................................... 11
Interface Descriptions ................................................................................................................................ 13
Registers and Memory ............................................................................................................................... 15
Transaction Scenarios ............................................................................................................................... 18
Requirements and Guidelines.................................................................................................................... 20
Chapter 3. Parameter Settings ............................................................................................................ 22
User Parameters Tab.......................................................................................................................................... 23
Buses ......................................................................................................................................................... 23
Address Decoding...................................................................................................................................... 24
Channels .................................................................................................................................................... 24
Memory Interfaces ..................................................................................................................................... 25
Generation Options .................................................................................................................................... 25
Synthesis Optimizations Tab............................................................................................................................... 25
Transfer Settings........................................................................................................................................ 26
Chapter 4. IP Core Generation............................................................................................................. 28
IP Core Generation in IPexpress ........................................................................................................................ 28
Licensing the IP Core................................................................................................................................. 28
Getting Started ........................................................................................................................................... 28
IPexpress-Created Files and Top Level Directory Structure...................................................................... 30
Simulation Evaluation................................................................................................................................. 31
Implementation Evaluation......................................................................................................................... 32
SGDMAC Core Implementation ................................................................................................................. 32
IP Core Implementation ............................................................................................................................. 33
Hardware Evaluation.................................................................................................................................. 34
Updating/Regenerating the IP Core ........................................................................................................... 34
IP Core Generation in Clarity Designer............................................................................................................... 35
Getting Started ........................................................................................................................................... 35
Clarity Designer Created Files and Top Level Directory Structure ............................................................ 39
Simulation Evaluation................................................................................................................................. 39
IP Core Implementation ............................................................................................................................. 40
Regenerating/Recreating the IP Core ................................................................................................................. 41
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 41
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 41
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Table of Contents
Chapter 5. Support Resources ............................................................................................................ 42
Lattice Technical Support.................................................................................................................................... 42
E-mail Support ........................................................................................................................................... 42
Local Support ............................................................................................................................................. 42
Internet ....................................................................................................................................................... 42
References.......................................................................................................................................................... 42
LatticeXP2.................................................................................................................................................. 42
LatticeECP3 ............................................................................................................................................... 42
ECP5.......................................................................................................................................................... 42
Revision History .................................................................................................................................................. 43
Appendix A. Resource Utilization ....................................................................................................... 44
LatticeECP3 FPGAs............................................................................................................................................ 44
Ordering Part Number................................................................................................................................ 44
LatticeXP2 FPGAs .............................................................................................................................................. 44
Ordering Part Number................................................................................................................................ 44
ECP5 LFE5U FPGAs .......................................................................................................................................... 44
Ordering Part Number................................................................................................................................ 44
ECP5 LFE5UM FPGAs ....................................................................................................................................... 45
Ordering Part Number................................................................................................................................ 45
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Scatter-Gather DMAC User Guide
Chapter 1:
Introduction
This user guide describes the Scatter-Gather Direct Memory Access Controller (SGDMAC) IP core for the ECP5™,
LatticeECP3™ and LatticeXP2™ families of devices. The Lattice SGDMAC core implements a configurable, multichannel, WISHBONE-compliant DMA controller with scatter-gather capability. Directions for specifying the IP
core’s configuration, including it in a user’s design, and directions for simulation and synthesis are provided in this
user’s guide.
Quick Facts
Table 1-1 gives quick facts about the Scatter-Gather DMA Controller IP core.
Table 1-1. Scatter-Gather DMA Controller IP Core Quick Facts
SGDMAC IP Configuration
16 Channel,
Dual-bus
Core
Requirements
Resource
Utilization
4 channel,
Dual-bus
FPGA Families
Supported
4 channel,
Dual-bus
LatticeECP3, LatticeXP2, ECP5
Targeted Device
LFE3-95EA-7FN672C
LFXP2-40E-6F672C
Data Path Width
32
32
LFE5U-85F-8BG756C LFE5UM-85F-8BG756C
32/64
32/8
LUTs
4311
3443
4049
3222
Slices
2670
2139
2570
1998
Registers
1932
1355
1637
1265
FMAX (MHz)
145
120
160
165
®
Lattice Implementation
Design Tool
Support
8 channel,
Dual-bus
Synthesis
Simulation
Lattice Diamond 3.4
Synopsys® Synplify Pro® for Lattice J-2014.09L
Mentor Graphics® Precision® RTL
Aldec® Active-HDL™ 9.3 SPI Lattice Edition
Mentor Graphics® ModelSim® SE 6.6e or later
Features
• Supports up to 16 physical channels
• Up to 8 sub-channels per physical channel
• Four priority levels using round-robin arbitration (weighted or simple)
• WISHBONE bus widths from 8 to 128 bits
• Simple DMA, split transfers, scatter-gather
• Direct interface to external RAM for packet buffering
• Autonomous and hardware-directed retry
• Supports WISHBONE burst and classic-cycle transfers
• Supports centralized and distributed DMA control architectures
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Chapter 2:
Functional Description
This chapter provides a functional description of the Scatter-Gather DMA Controller core.
Key Concepts
Direct Memory Access (DMA) is a technique for transferring blocks of data between system memory and peripherals without a processor (e.g., system CPU) having to be involved in each transfer. DMA not only offloads a system’s processing elements, but can transfer data at much higher rates than processor reads and writes.
Scatter-Gather DMA provides data transfers from one non-contiguous block of memory to another by means of a
series of smaller contiguous-block transfers.
Buffer Descriptors hold the necessary control information for data transfers:
• Source and destination buses and addresses
• Amount of data to be transferred and maximum burst size
• Addressing modes, bus sizes, transaction types, retry options, etc.
Buffer descriptors may be chained together to provide scatter-gather capability.
A DMA Channel consists of:
• A set of Buffer Descriptors describing the transfers associated with the channel
• Control and status registers for initiating/observing the transfer process
• An interface to allow the DMA engine access to the channel control and status
• An optional external DMA request/acknowledge signal pair for hardware initiated transfers
• A signal for indicating a pending DMA request to the DMA controller’s arbiter and engine
The SGDMAC core provides DMA transfers of data between WISHBONE bus slaves for up to 16 physical DMA
channels.
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Functional Description
Block Diagram
The high-level architecture of the Scatter-Gather DMA Controller is shown in Figure 2-1.
Figure 2-1. SGDMAC Block Diagram
WISHBONE
Slave
WISHBONE
Master A
channel 1
Channel Arbiter
DMA Request/
Acknowledge
channel 0
BDRAM
Interface
Buffer
Description
RAM
PBUFF
Interface
Packet
Buffer
DMA
Engine
channel N-1
EVENT
ERROR
Control/
Status
WISHBONE
Master B
WISHBONE Interfaces
The SGDMAC core provides a single WISHBONE slave for accessing registers and memory within the core itself.
The slave does full or partial address decoding depending on the FULL_ADDR_SIZE parameter. If greater than
zero, the upper FULL_ADDR_SIZE bits must match the FULL_ADDR parameter value. If FULL_ADDR_SIZE is
zero, the slave address range is being decoding externally, and an active-high scyc input indicates a valid cycle.
The core may be configured with either one or two WISHBONE masters. The bus masters are controlled by the
DMA Engine. Each master is capable of interacting with both burst-capable and non-burst slaves. Full or partial
width bus interactions are allowed (configured in the buffer descriptor).
Control and Status
Channel control and status registers are accessible through the WISHBONE slave. The registers contain control
and current state information for each channel (up to 16 channels). Register details are provided in the Registers
and Memory section of this document. Only the registers required for NUM_CHAN channels are implemented in
the core.
The control and status block also handles external DMA request and acknowledge signals. Each channel control
and status register is connected to a single pair of request/acknowledge signals. DMA requests may be generated
by hardware via the request signal or by writing the request bit in the channel control and status register.
The control and status block also contains two interrupt registers per channel: one for event interrupts (such as
transfer complete notification), the other for errors. Interrupt source registers hold the event until cleared through
the slave interface.
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Functional Description
Channel Arbiter
The channel arbiter determines which channel DMA request will be serviced next. For weighted round-robin arbitration, the arbiter consists of four round-robin arbiters, one for each of four priority levels. Each DMA channel
makes an appearance on one of the round-robin arbiters as determined by a “priority group” field in its control register. Each of the four round-robin arbiters will handle NUM_CHAN channels.
The four round-robin arbiters feed a fifth weighted-share arbiter. Each priority group receives a share of the arbiter’s attention that is proportional to the value (0 is lowest, 15 is highest) entered in its “share” control register field.
The weights correspond to numbers of transactions without regard to the total amount of data transferred.
Simple round-robin arbitration employs a single NUM_CHAN-wide round-robin arbiter.
Once the transaction on the active channel is under way, the arbiter is released to choose the next active channel.
This arbiter look-ahead feature minimizes the transaction startup latency.
The Global Arbiter control register provides the ability to mask a channel from vying for active channel status.
Masking a channel, in effect, freezes a channel in its current state.
BDRAM Interface
Buffer descriptors are held in an external dual port RAM. The BDRAM interface provides independent read and
write access. Reads require a data valid signal to be returned from the BD memory, since the read latency is
unknown. Writes require no acknowledgement. The BDRAM is read-write accessible via the WISHBONE slave.
Each channel buffer descriptor head pointer is set in the channel control and status register. Buffer descriptor integrity is the responsibility of the software; the hardware does no checking.
PBUFF Interface
The SGDMAC core optionally provides an interface to an external packet buffer. The interface is a simple memory
interface with separate address and data buses for reads and writes. The Packet Buffer may serve as the source or
destination for DMA transactions. The contents of Packet Buffer memory are accessible through DMA transfers, not
directly accessible through the SGDMAC WISHBONE slave interface.
DMA Engine
The DMA Engine uses information stored in the channel buffer descriptors and channel control registers to control
the operation of the WISHBONE bus masters. The DMA engine supports the following transactions:
Simple DMA
Simple DMA transfers are block copies of data from the source address to the destination address. These may be
intra- or inter-bus transfers. The active channel remains the active channel until the entire transfer is complete.
Multi-Burst Transfers
Large blocks of data may have to be split into bursts to avoid bus-hogging by individual channels or priority groups.
The maximum burst size is specified by a field in the buffer descriptor. The DMA engine transfers the burst, then
tells the channel and channel arbiter that the burst has been transferred. The channel then must compete for attention according to the usual arbitration scheme. When all bursts have been transferred, the channel and channel
arbiter are notified, and normal operation resumes. Inter-bus bursts are always locked.
Multi-Descriptor Transfers
Scatter-Gather operation is implemented using multi-descriptor transfers. A bit in the buffer descriptor tells the
DMA engine whether the descriptor is the last in a series. Each descriptor has its own transfer size, burst size,
source and destination addresses. When the current burst is complete, the DMA engine fetches the next buffer
descriptor, if there is one. The arbiter’s look-ahead feature minimizes the time required between descriptors.
Split Transactions
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Functional Description
Any of the transaction types discussed above may be implemented as split transactions. Split transaction bursts
occur in two steps: source to packet buffer, and packet buffer to destination. The advantage offered by split transactions is that each step only occupies one bus. The channel logic maintains the to-packet-buffer/from-packet-buffer
sequence. The software subsystem is responsible for ensuring buffer offsets and burst sizes are set appropriately
to prevent channel data overlap.
Direct Packet Buffer Transactions
The Packet Buffer may be selected as the source or destination for simple DMA transactions by setting the
SRC_BUS or DST_BUS field in the buffer descriptor. When the packet buffer is the source (or destination), the corresponding address in the buffer descriptor is ignored; the channel packet buffer offset is used instead.
Delayed Transactions
Delayed transactions occur when a source or destination WISHBONE slave signals a retry in response to the
access request from the SGDMAC. Depending on the state of the RETRY bit in the buffer descriptor, the SGDMAC
either: if RETRY is set, relinquishes control and re-attempts to become the active channel; or, relinquishes control,
clears its DMA_REQUEST bit, and waits for the delayed peripheral to activate the channel’s dma request input. It’s
the responsibility of the peripheral to activate the request only when it can respond without retry. The number of
retries is determined by the NUM_RETRY field in the channel control and status register. Exceeding NUM_RETRY
results in an error. See the sections on Autonomous Retry and Hardware Retry below.
EOD Transactions
For some transactions, the data source may not have available the number of bytes designated by the buffer
descriptor. The SGDMAC core uses a WISHBONE data tag (user-defined set of signals synchronous with the
WISHBONE slave output data) to signal EOD to the master requesting the data. In response to the EOD tag, the
WISHBONE master terminates the cycle and signals the DMA engine. The DMA engine signals transfer complete
to the channel logic and arbiter.
Errored Transactions
The scope of error checking by the SGDMAC core is limited to its field of view. For example, address values, transfer sizes, buffer descriptor memory allocation and alignment, and packet buffer overlap are conditions that the core
(by design) lacks the information to detect and address. It is the responsibility of the configuration software to
ensure control information integrity.
The core is able to detect bus errors and retry errors. Transactions that encounter errors freeze the active channel
state. The channel will not vie to become the active channel again until the errors have been cleared and the channel reset (by disabling and enabling it).
Freezing Channels
Channels may be prevented from vying for active channel status by way of the GARBITER.CHARBMSK bits. A
channel with its corresponding CHARBMSK bit set has its arbiter request bit masked. Because the channel never
becomes the active channel, it remains in its current state. Note that this differs from disabling a channel, which
returns the channel logic to its initialization state.
Bus Locking
Setting the LOCK bit in the buffer descriptor causes the WISHBONE master to request a locked transfer. Inter-bus,
non-split transfers are always locked. Intra-bus and split transfers are locked only if LOCK is set.
Buffer Status Mode
Setting the BUFFER_STATUS user parameter to ‘1’ provides logic for checking and updating buffer availability. In
this mode, the CONFIG0.BD_STATUS_EN bit enables status checking. If ‘1’, the DMA engine checks
CONFIG0.BD_STATUS. A ‘1’ indicates that the requested buffer is available: the transfer proceeds as usual, and
the dma_engine clears CONFIG0.BD_STATUS upon completion of the transfer. If CONFIG0.BD_STATUS is ‘0’, the
requested buffer is unavailable, the channel’s buffer descriptor error bit is set, and the transfer is terminated. If
CONFIG0.BD_STATUS_EN is ‘0’, the buffer status check is skipped, and the transfer proceeds as usual.
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Functional Description
AUXCTRL and AUXSTAT
The optional auxctrl and auxstat ports provide auxiliary read (auxstat) and write (auxctrl) capability. The read-only
auxstat port operates in pass-through mode - that is, there are no registers associated with the port. The write-only
auxctl port is only active during a slave write, zeros otherwise.
Memory Interfaces: The “Number of Buffer Descriptors” option configures the size of the BD (buffer descriptor)
memory read and write address buses. There are four 32-bit words per buffer descriptor. 256 is the maximum number of descriptors allowed. The “Packet Buffer Size” option is the number of bytes in the external packet buffer. This
item sets the packet buffer address bus sizes. The data bus is always the size of the largest WISHBONE bus.
Primary I/O
The top-level interface diagram is shown in Figure 2-2 and a brief description of the signals is given in Table 2-1.
Figure 2-2. SGDMAC Core Primary I/O
SLAVE
a_addr[ ]
a_wdat[ ]
a_rdat[ ]
a_sel[ ]
a_we
a_cyc
a_lock
a_stb
a_ack
a_err
a_retry
a_eod
saddr[ ]
swdat[ ]
srdat[ ]
ssel[ ]
swe
scyc
sstb
sack
serr
sretry
d_waddr[ ]
bd_wdat[ ]
bd_we
bd_raddr[ ]
bd_rdat[ ]
bd_rval
dma_req[ ]
dma_ack[ ]
clk
rstn
BD INTF
MASTER A
SGDMAC
PB INTF
9
b_addr[ ]
b_wdat[ ]
b_rdat[ ]
b_sel[ ]
b_we
b_cyc
b_lock
b_stb
b_ack
b_err
b_retry
b_eod
actchan[ ]
subchan[ ]
pb_write
pb_wdat[ ]
pb_waddr[ ]
pb_raddr[ ]
pb_rdat[ ]
event[ ]
error[ ]
auxctrl[ ]
auxstat[ ]
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Scatter-Gather DMAC User Guide
Functional Description
Table 2-1. Top-Level Port Definitions
Port
Size
I/O
Description
clk
1
I
System clock
rstn
1
I
System wide asynchronous active-low reset signal.
a_addr
AWIDTH
O
A-Bus master address output
a_wdat
DWIDTHA
O
A-Bus master write data
Global Signals
A-Bus Master Signals
a_rdat
DWIDTHA
I
A-Bus master read data
a_sel
DWIDTHA/8
O
A-Bus master byte selects, active high
a_we
1
O
A-Bus master write enable output, active high
a_cyc
1
O
A-Bus master valid transfer cycle output, active high
a_lock
1
O
A-Bus master lock request to bus arbiter
a_stb
1
O
A-Bus master data strobe output, active high
a_cti
3
O
A-Bus master cycle type identifier, active high
a_ack
1
I
A-Bus master acknowledge, active high
a_err
1
I
A-Bus master error acknowledge, active high
a_retry
1
I
A-Bus master retry, active high
a_eod
1
I
A-Bus master end-of-data flag
b_addr
AWIDTH
O
B-Bus master address output
b_wdat
DWIDTHB
O
B-Bus master write data
B-Bus Master Signals
b_rdat
DWIDTHB
I
B-Bus master read data
b_sel
DWIDTHB/8
O
B-Bus master byte selects, active high
b_we
1
O
B-Bus master write enable output, active high
b_cyc
1
O
B-Bus master valid transfer cycle output, active high
b_lock
1
O
B-Bus master lock request to bus arbiter
b_stb
1
O
B-Bus master data strobe output, active high
b_cti
3
O
B-Bus master cycle type identifier, active high
b_ack
1
I
B-Bus master acknowledge, active high
b_err
1
I
B-Bus master error acknowledge, active high
b_retry
1
I
B-Bus master retry, active high
b_eod
1
I
B-Bus master end-of-data flag
saddr
AWIDTH
I
Slave address input
swdat
32
I
Slave write data
srdat
32
O
Slave read data
ssel
4
I
Slave byte selects, active high
swe
1
I
Slave write enable input, active high
scyc
1
I
Slave valid transfer cycle input, active high
sstb
1
I
Slave data strobe input, active high
sack
1
O
Slave acknowledge, active high
serr
1
O
Slave error acknowledge, active high
sretry
1
O
Slave retry, active high
BD_AWIDTH
O
Buffer descriptor write address
Slave Signals
Buffer Descriptor Memory Interface
bd_waddr
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Functional Description
Table 2-1. Top-Level Port Definitions (Continued)
Port
Size
I/O
bd_wdat
32
O
Buffer descriptor write data
bd_we
1
O
Buffer descriptor write enable, active high
bd_re
1
O
Buffer descriptor read request, active high
bd_raddr
Description
BD_AWIDTH
O
Buffer descriptor read address
bd_rdat
32
I
Buffer descriptor read data
bd_rval
1
I
Buffer descriptor read data valid
bd_err
1
O
Buffer status check error
1
O
Packet buffer write enable, active high
pb_wdat
DWIDTHA
O
Packet buffer write data
pb_waddr
PB_AWIDTH
O
Packet buffer write address
pb_raddr
PB_AWIDTH
O
Packet buffer read request, active high
pb_rdat
DWIDTHA
I
Packet buffer read data
pb_rval
1
I
Packet buffer read data valid
Packet Buffer Interface
pb_write
Interrupt and Control
dma_req[]
NUM_CHAN
I
DMA requests, active high
dma_ack[]
NUM_CHAN
O
DMA acknowledge, active high
event[]
NUM_CHAN
O
Event interrupts
error[]
NUM_CHAN
O
Error interrupts
actchan[]
CWIDTH
O
Active channel number
subchan[]
SUBWIDTH
O
Sub-channel value
auxctrl[]
16
O
Auxiliary control outputs
auxstat[]
16
I
Auxiliary control inputs
System Configurations
Single-WISHBONE
A typical single-WISHBONE configuration is illustrated in Figure 2-3.
Figure 2-3. SGDMAC in a Single-WISHBONE System
LOCALBUS/WISHBONE
BRIDGE
SLAVE
MEMORY
MASTER
INTERFACE
WISHBONE BUS
SLAVE
MASTER
SGDMAC
REQ/ACK
BD_IF
PB_IF
BD
RAM
PACKET
BUFFER
WISHBONE
WISHBONE
INTERFACE
INTERFACE
PERIPHERAL
PERIPHERAL
The SGDMAC core Master and Slave interfaces are connected to the WISHBONE bus. The SLAVE data width is
always 32 bits. The MASTER data width should be the full width of the bus. Single-bus configurations require a
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Functional Description
Packet Buffer, since all intra-bus transfers are implemented as split transactions. The SGDMAC Master competes
with other bus masters for bus ownership. Peripherals are connected to the WISHBONE bus by their slave (and
perhaps master) interfaces, and may also have request/acknowledge connections to the SGDMAC to allow peripheral-initiated transfers.
Peripherals need not occupy the full bus width; if not, they should be connected to the low-order WISHBONE data
signals for both Big- and Little-Endian systems (for example, an eight-bit port would connect to D0-D7). Transfers
between slaves with dissimilar port widths are handled by the SGDMAC core. For example, for a data transfer from
an 8-bit peripheral to a 32-bit peripheral, the read portion of the transfer would occur 8 bits at a time, the write portion 32 bits at a time. Transfers to and from WISHBONE slaves should always utilize their full bus widths, both to
achieve the greatest throughput and to avoid confusion about which portion of the bus should be active (especially
in Big-Endian systems).
Dual-WISHBONE
A typical dual-WISHBONE configuration is illustrated in Figure 2-4.
Figure 2-4. SGDMAC in a Dual-WISHBONE System
LOCALBUS/WISHBONE
BRIDGE
MEMORY
INTERFACE
SLAVE MASTER
WISHBONE BUS A
SLAVE MASTER_A
SGDMAC
BD_IF
BD
RAM
PB_IF
REQ/ACK
PERIPHERAL
PERIPHERAL
WISHBONE
INTERFACE
WISHBONE
INTERFACE
MASTER_B
PACKET
BUFFER
WISHBONE BUS B
Higher throughput may be achieved by adding a second WISHBONE bus. A dual-bus SGDMAC core performs
both intra- and inter-bus transfers. The same bus-width considerations apply for dual-bus configurations as for single-bus. The two WISHBONE buses need not be of the same topology; for example, one may be a shared bus and
the other a crossbar switch. They do, however, need to have the same Endian-ness.
Inter-bus transfers do not require split transactions. Unlike intra-bus transfers, inter-bus transfers do not use Packet
Buffer resources (in fact, the Packet Buffer is optional if only inter-bus transfers are required). A small FIFO in the
SGDMAC core provides temporary storage for assembly/disassembly of data transferred from bus to bus. For nonsplit transfers, both buses are owned by the SGDMAC for the duration of each burst. Split transactions, on the other
hand, transfer a full burst of data from the source bus to the Packet buffer, then from the Packet Buffer to the destination bus, and only occupy one bus at a time. Bus traffic characteristics will determine whether split or non-split
transactions provide the greatest overall throughput.
Distributed DMA
The single- and dual-bus configurations above are examples of centralized DMA control: a single controller handles
the DMA transfers for a set of WISHBONE peripherals. For some systems, a better solution might be to distribute
the DMA function to the bus clients themselves, allowing them to initiate and accept transfers to and from other clients. This approach offers the following advantages:
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Functional Description
• Reduces bus traffic. In a centralized DMA system, two bus transactions are required for each datum moved. With
distributed DMA, most data transfers require only one bus transaction.
• The number of available DMA channels grows with the addition of each DMA-capable peripheral.
• Supports full-interconnect bus topologies (crossbar switch, for example) for higher throughput. Multiple bus master-slave pairs can exchange data simultaneously.
The SGDMAC core provides an easy way to add DMA capability to peripheral devices by using the Packet Buffer
interface and the request/acknowledge ports. A possible implementation of a DMA-enabled peripheral is illustrated
in Figure 2-5.
Figure 2-5. DMA-Capable Peripheral with SGDMAC Core
WISHBONE BUS
SLAVE MASTER
WISHBONE
SGDMAC
BD_IF
BD
RAM
INTERFACE
REQ/ACK
PB_IF
PERIPHERAL
DUAL PORT
RAM
SLAVE
PERIPHERAL
The SGDMAC core in this example is used in single-bus mode, although dual-bus mode would also work (the
peripheral could transfer data between itself and either bus). A small buffer descriptor RAM provides only those
descriptors needed by the peripheral. A dual-port RAM attached to the core’s Packet Buffer interface provides the
data path, and the request/acknowledge signals allow the peripheral to initiate transfers and recognize transfer
completion. The core’s slave interface may be connected to the wishbone bus for channel and buffer descriptor
setup or, for smart peripherals, there might be a direct connection between the peripheral and the core’s slave port.
Interface Descriptions
WISHBONE Interfaces
All WISHBONE interfaces are compliant with WISHBONE Specification B.3. The Cycle Indicator tags are used for
burst transactions. They are sourced by the WISHBONE masters and valid when the strobe signal (stb) is active.
The SGDMAC WISHBONE master interfaces also support an End-Of-Data tag. Buffer Descriptor Interface. The
eod signal may be returned by bus slaves and is valid when the acknowledge (ack) signal is active.
Buffer Descriptor Memory Interface
The interface to the buffer descriptor RAM uses a simple synchronous handshake for reads and writes, as shown in
Figure 2-6.
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Functional Description
Figure 2-6. Buffer Descriptor Interface Timing
clk
bd_raddr[ ]
A0
A1
A2
A3
BD0
BD1
Ar
bd_re
bd_rdat[ ]
BD2
BDr
BD3
bd_rval
bd_waddr[ ]
bd_wdat[ ]
Aw
BDw
bd_we
The SGDMAC core fetches a sequence of four 32-bit words from the user-provided Buffer Descriptor memory
using a four clock-cycle burst. The active-high bd_re signal, accompanied by a read address on bd_raddr, signals
the read request. The BD memory responds with an active-high bd_rval, accompanied by buffer descriptor data.
The request-to-valid-data interval is under the control of the BD memory. WISHBONE slave initiated reads are presented to the Buffer Descriptor memory as active high bd_re and bd_raddr, both of which are held until the BD
memory responds with an active-high bd_rval and corresponding data. BD memory writes are presented as a single clock-cycle assertion of bd_we accompanied by write address bd_waddr and write data bd_wdat. The SGDMAC core assumes that the BD memory accepts the write, so no acknowledge signal is required.
Packet Buffer Interface
The interface to the external Packet Buffer memory also uses a simple handshake to transfer data, as shown in
Figure 2-7.
Figure 2-7. Packet Buffer Interface Timing
clk
pb_raddr[ ]
A0
A1
A2
A3
pb_read
D0
pb_rdat[ ]
D1
D2
D3
pb_rval
Packet Buffer Read
pb_wdat[ ]
D0
D1
pb_waddr[ ]
A0
A1
D2
D3
A2
A3
pb_write
Packet Buffer Write
The pb_read signal is asserted along with the read address. The PB memory responds some number of clockcycles later with pb_rval and the read data.
Note: Because the PB memory’s read latency is unknown to the core, the SGDMAC may perform more reads than
necessary to complete the burst. The data from these superfluous reads are unused, and the next burst will begin
at the appropriate PB read address. This should note pose a problem for Packet Buffers implemented as normal
RAMs, but prevents the use of Packet Buffers implemented as FIFOs.
For packet buffer writes, the pb_write signal is asserted with the write address and data. The SGDMAC core
assumes that the PB memory can accept the write, so no acknowledge signal is required.
IPUG67_1.8, March 2015
14
Scatter-Gather DMAC User Guide
Functional Description
Registers and Memory
Table 2-2. Registers and Memory
Name
Addr (hex)
Width
Access
Description
IPID
0
32
R
IP identification register
IPVER
4
32
R
IP version register
GCONTROL
8
32
RW
Global control register
GSTATUS
c
32
RW
Global status register
Global Registers
GEVENT
10
32
RC1
Global channel event register and mask
GERROR
14
32
RW
Global channel error register and mask
GARBITER
18
32
RW
Global arbiter control register
GAUX
1c
32
RW
Auxiliary inputs and outputs
CONTROLN
N
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