EDGE-DET-X2-U1

2D Edge Detector IP Core User’s Guide February 2011 IPUG86_01.0 Table of Contents Chapter 1. Introduction .......................................................................................................................... 3 Quick Facts ........................................................................................................................................................... 3 Features ................................................................................................................................................................ 3 Chapter 2. Functional Description ........................................................................................................ 4 Key Concepts........................................................................................................................................................ 4 Block Diagram....................................................................................................................................................... 4 Active Region Selection ........................................................................................................................................ 5 Interface Descriptions ........................................................................................................................................... 6 Video Input/Output ....................................................................................................................................... 6 Parameter Update Port ................................................................................................................................ 6 Chapter 3. Parameter Settings .............................................................................................................. 7 User Parameters Tab............................................................................................................................................ 8 Video Frame................................................................................................................................................. 8 Edge Detection Method................................................................................................................................ 9 Data Widths.................................................................................................................................................. 9 Implementation Options ............................................................................................................................... 9 Performance options .................................................................................................................................... 9 Chapter 4. IP Core Generation............................................................................................................. 10 Licensing the IP Core.......................................................................................................................................... 10 Getting Started .................................................................................................................................................... 10 IPexpress-Created Files and Top Level Directory Structure............................................................................... 12 Instantiating the Core .......................................................................................................................................... 13 Running Functional Simulation ........................................................................................................................... 13 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 14 Hardware Evaluation........................................................................................................................................... 15 Enabling Hardware Evaluation in Diamond................................................................................................ 15 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 15 Updating/Regenerating the IP Core .................................................................................................................... 15 Regenerating an IP Core in Diamond ........................................................................................................ 15 Regenerating an IP Core in ispLEVER ...................................................................................................... 16 Chapter 5. Support Resources ............................................................................................................ 17 Lattice Technical Support.................................................................................................................................... 17 Online Forums............................................................................................................................................ 17 Telephone Support Hotline ........................................................................................................................ 17 E-mail Support ........................................................................................................................................... 17 Local Support ............................................................................................................................................. 17 Internet ....................................................................................................................................................... 17 References.......................................................................................................................................................... 17 LatticeECP2/M ........................................................................................................................................... 17 LatticeECP3 ............................................................................................................................................... 17 LatticeXP2.................................................................................................................................................. 17 Revision History .................................................................................................................................................. 17 Appendix A. Resource Utilization ....................................................................................................... 18 LatticeECP3 Devices .......................................................................................................................................... 18 Ordering Part Number................................................................................................................................ 18 LatticeECP2M Devices ....................................................................................................................................... 18 Ordering Part Number................................................................................................................................ 18 LatticeXP2 Devices ............................................................................................................................................. 19 Ordering Part Number................................................................................................................................ 19 © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG86_01.0, February 2011 2 2D Edge Detector IP Core User’s Guide Chapter 1: Introduction The 2D Edge Detector IP core detects edges in incoming video frames using the Sobel or Prewitt algorithms. Its flexible architecture supports a wide variety of video frame sizes on LatticeECP2M™, LatticeXP2™, and LatticeECP3™ devices. A simple I/O handshake makes the core suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in-system via a simple memory interface. Dynamic zoom and pan functions are optionally provisioned at compile time. Quick Facts Table 1-1 gives quick facts about the 2D Edge Detector IP core. Table 1-1. Quick Facts 2D Edge Detector IP Core 320x240 Core Requirements FPGA Fa miles Supported LUTs/Registers 1280x720 LatticeXP2, LatticeECP2M, LatticeECP3 456/393 277/119 465/399 475/399 1 1 1 2 EBRs sysDSP™ blocks 0 5 0 0 456/393 277/119 465/399 475/399 EBRs 1 1 1 2 sysDSP blocks 0 5 0 0 LUTs/Registers LUTs/Registers LatticeECP2M LatticeECP3 437/391 274/119 462/398 460/402 EBRs 1 1 1 2 sysDSP blocks 0 10 0 0 Lattice Diamond™ 1.1 or ispLEVER® 8.1SP1 Lattice Implementation Design Tool Support 720x480 Minimum Device Required LatticeXP2 Resource Utilization 640x4801 Synopsys® Synplify™ Pro for Lattice D-2010.03L-SP1 Synthesis Aldec® Active-HDL™ 8.2 Lattice Edition II Simulation Mentor Graphics® ModelSim™ SE 6.3F 1. Uses sysDSP blocks for adder functions. Features • Single color plane input • Configurable input data width • Dynamically variable input frame size • Dynamic active region selection • Dynamic selection between Sobel and Prewitt algorithms • Dynamic detection threshold modification IPUG86_01.0, February 2011 3 2D Edge Detector IP Core User’s Guide Chapter 2: Functional Description Key Concepts Video edge detection is the process of calculating gradients (rates of change) in pixel values in an incoming frame. If the gradient at a given pixel location exceeds a threshold value, the edge detector outputs a ‘1’, ‘0’ otherwise. For the Sobel and Prewitt algorithms, gradients are calculated using convolution filters with 3x3 windows with fixed coefficient values. The coefficient values are 0, 1, -1, and 2, so multiplication operations are performed using simple shifts and inversions. The 2D Edge Detector IP core simultaneously applies two orthogonal 3x3 gradient filters to its input pixel stream and sums the results. The Sobel gradient filter kernels are separable, and have the following fixed values: -1 0 * [1 2 1] 1 and 1 2 * [ -1 0 1 ] 1 The Prewitt filter kernels are also separable, with the following fixed values: 1 1 * [ -1 0 1 ] 1 and 1 0 * [ 1 1 1 ] 1 Block Diagram The high-level architecture of the 2D Edge Detector core is diagrammed in Figure 2-1. Figure 2-1. 2D Edge Detector IP Core Block Diagram dvalid_in frmsync_in Windowing Logic Line Buffers din[ ] ready pwrite paddr[ ] pwdat[ ] Dynamic Parameters Registers Active Region Selection Coefficient Selection prdat [ ] Multiply-Add Threshold Logic dout frmsync_out dvalid_out IPUG86_01.0, February 2011 4 2D Edge Detector IP Core User’s Guide Lattice Semiconductor Functional Description Input data is stored in line buffers, then passed to windowing logic for edge mode handling and data alignment. Optional control inputs allow real-time specification of the portion of the input frame used to generate output pixels (referred to as the “active region”). Windowed data and coefficients are sent to the arithmetic unit which multiplies the data values by their corresponding coefficients and sums the multiplication results. Horizontal and vertical gradients are calculated, their outputs are summed, and then the sum is compared to the value on the core’s threshold input. Values exceeding the threshold result in a ‘1’ on the dout output port, which is ‘0’ otherwise. Active Region Selection The 2D Edge Detector may be configured to allow the user to dynamically alter the coordinates of the active region of the input frame. The active region concept is illustrated in Figure 2-2. Figure 2-2. 2D Edge Detector IP Core Active Regions 0,0 upleftX, upleftY Active Region upleftX+actwidth, upleftY+actheight VWIDTH_IN, VHEIGHT_IN The upleftX and upleftY ports set the coordinates of the first pixel in the input frame that will have a corresponding pixel in the output frame. The actwidth and actheight ports determine the region of pixels in the input frame that will have corresponding pixels in the output frame. Both sets of inputs – upleft, and active region – are synchronized internally and delivered to the core logic at the appropriate time to avoid anomalies when moving from frame to frame. Primary I/O Table 2-1. Primary I/O Port Size I/O Description Global Signals clk 1 I System clock rstn 1 I Asynchronous reset, active low clken 1 I Clock enable, active high (optional) srst 1 I Synchronous reset, active high (optional) 1 O Core is ready for input Video Input ready dvalid_in 1 I Input valid frmsync_in 1 I Frame sync, current pixel is row 0, column 0 DWIDTH I Pixel data in din[ ] Video Output IPUG86_01.0, February 2011 5 2D Edge Detector IP Core User’s Guide Lattice Semiconductor Functional Description Table 2-1. Primary I/O (Continued) Port Size I/O 1 O dvalid_out Description Output valid frmsync_out 1 O Frame sync out, marks row 0, column 0 dout 1 O Edge data out pwrite 1 I Parameter write paddr 4 I Parameter address Parameter Update Port pwdat I Parameter write data prdat O Parameter read data Miscellaneous tags_in TAGS_WIDTH tags_out TAGS_WIDTH Interface Descriptions Video Input/Output The 2D Edge Detector uses a simple handshake to pass pixel data into the core. The core asserts its ready output when it is ready to receive data. When the driving module has data to give the core, it drives the core’s dvalid_in port to a ‘1’ synchronously with the rising edge of the clk signal, providing the input pixel data on port din. The frmsync_in input should be driven to a ‘1’ during the clock cycle when the first pixel of the first row in the incoming video frame is active. Correspondingly, dvalid_out is active when valid edge data is available on dout, and frmsync_out marks the first pixel, first row of the output video frame. Parameter Update Port The parameter update port is provided when the user enables dynamic update for any of the following: input frame size, active region size and location, edge detection method, or edge detection threshold. The port consists of an active-high write enable, pwrite; a four-bit register address, paddr; write data, pwdat; and read data, prdat. When pwrite is a ‘1’, the register selected by paddr is written with the value of pwdat. The read output prdat always carries the value of the register selected by paddr. The register addresses are as follows: • 0 – input video frame width • 1 – input video frame height • 2 – x coordinate of upper left corner of active region • 3 – y coordinate of upper left corner of active region • 4 – width of active region (minus 1) • 5 – height of active region (minus 1) • 6 – edge detection algorithm (0 is Sobel, 1 is Prewitt) • 7 – edge detection threshold • 8 – update control (write to ‘1’ to pass new values to the windowing function; the core will clear update_control when the windowing function has begun using the new values) IPUG86_01.0, February 2011 6 2D Edge Detector IP Core User’s Guide Chapter 3: Parameter Settings The IPexpress™ tool is used to create IP and architectural modules in the Diamond or ispLEVER software. Refer to “IP Core Generation” on page 10 for a description of how to generate the IP. The 2D Edge Detector IP core can be customized to suit a specific application by adjusting parameters prior to core generation. Since the values of some parameters affect the size of the resultant core, the maximum value for these parameters may be limited by the size of the target device. Table 3-1 provides the list of user configurable parameters for the 2D Edge Detector IP core. Table 3-1. Edge Detector Parameters Parameter Range Default Video Frame In and Out Input Data Width 4 to 24 8 Frame Width In 200 to 2000 320 Frame Hight In 100 to 1200 240 1 to 703 320 24 to 1200 240 0 to ACTWIDTH-1 0 Active Region Width Active Region Height Upper Left X Coordinate of Active Region Upper Left Y Coordinate of Active Region 0 to ACTHEIGHT-1 0 Edge Mode VALUE, COPY, MIRROR COPY Edge Value 0 to 1 Regenerate IP/Module. 2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. 4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension. 5. Click Next. The IP core’s dialog box opens showing the current option settings. 6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG86_01.0, February 2011 16 2D Edge Detector IP Core User’s Guide Chapter 5: Support Resources Lattice Technical Support There are a number of ways to receive technical support as listed below. Online Forums The first place to look is Lattice Forums (www.latticesemi.com/support/forums.cfm). Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers. Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m. Pacific Time. • For USA and Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • techsupport@latticesemi.com • techsupport-asia@latticesemi.com Local Support Contact your nearest Lattice sales office. Internet www.latticesemi.com References LatticeECP2/M • HB1003, LatticeECP2/M Family Handbook LatticeECP3 • HB1009, LatticeECP3 Family Handbook LatticeXP2 • DS1009, Lattice XP2 Datasheet Revision History Date Document Version IP Core Version February 2011 01.0 1.0 IPUG86_01.0, February 2011 Change Summary Initial release. 17 2D Edge Detector IP Core User’s Guide Appendix A: Resource Utilization This appendix gives resource utilization information for Lattice FPGAs using the 2D Edge Detector IP core. The IP configurations shown in this chapter were generated using the IPexpress software tool. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond and ispLEVER help systems. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com. LatticeECP3 Devices Table A-1. Performance and Resource Utilization1, 2 Frame Size DWIDTH DSP Adders LUTs Slices PFU Registers EBRs 320x240 8 No 540 368 397 1 DSP Slices fMAX (MHz) 0 226 640x480 8 Yes 399 295 203 1 60 168 720x480 8 No 528 351 403 1 0 204 1280x720 8 No 528 352 407 2 0 154 1. Performance and utilization data are generated targeting an LFE3-70EFPBGA672 device using Diamond 1.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. 2. PAR settings:  Placement Effort Level: 5 Routing Passes: 6 Placement Iterations: 3 Routing Delay Reduction Passes: 1 PLC Input Limit: Low Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeECP3 devices is EDGE-DET-E3-U1. LatticeECP2M Devices Table A-2. Performance and Resource Utilization1, 2 Frame Size DWIDTH DSP Adders LUTs Slices PFU Registers EBRs 320x240 8 No 559 386 398 1 DSP Slices fMAX (MHz) 0 190 640x480 8 Yes 408 296 203 1 40 173 720x480 8 No 530 353 402 1 0 209 1280x720 8 No 553 368 410 2 0 191 1. Performance and utilization data are generated targeting an LFE2M35E-6F672C device using Diamond 1.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family. 2. PAR settings: defaults. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeECP2M devices is  EDGE-DET-PM-U1. IPUG86_01.0, February 2011 18 2D Edge Detector IP Core User’s Guide Lattice Semiconductor Resource Utilization LatticeXP2 Devices Table A-3. Performance and Resource Utilization1, 2 Frame Size DWIDTH DSP Adders LUTs 320x240 640x480 Slices PFU Registers EBRs DSP Slices fMAX (MHz) 8 No 559 386 398 1 0 155 8 Yes 408 296 203 1 40 153 720x480 8 No 530 353 402 1 0 161 1280x720 8 No 553 368 410 2 0 170 1. Performance and utilization data are generated targeting an LFXP2-40E-6F672Cdevice using Diamond 1.1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. 2. PAR settings: defaults. Ordering Part Number The Ordering Part Number (OPN) for the 2D Edge Detector IP core on LatticeXP2 devices is EDGE-DET-X2-U1. IPUG86_01.0, February 2011 19 2D Edge Detector IP Core User’s Guide